1 /**
2 ******************************************************************************
3 * @file rtl8721d_vector.h
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file contains all the functions prototypes for the IRQ firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * This module is a confidential and proprietary property of RealTek and
13 * possession or use of this module requires written permission of RealTek.
14 *
15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
16 ******************************************************************************
17 */
18
19 #ifndef _RTL8710B_VECTOR_TABLE_H_
20 #define _RTL8710B_VECTOR_TABLE_H_
21
22 /** @addtogroup AmebaD_Platform
23 * @{
24 */
25
26 /** @defgroup IRQ
27 * @brief IRQ modules
28 * @{
29 */
30
31 /** @addtogroup IRQ
32 * @verbatim
33 *****************************************************************************************
34 * Introduction
35 *****************************************************************************************
36 * IRQ table, please refer to IRQ Exported Constants->IRQn_enum->IRQn
37 *
38 *****************************************************************************************
39 * how to use
40 *****************************************************************************************
41 * 1. register/unregister IRQ use: InterruptRegister/InterruptUnRegister
42 * 2. enable/disable IRQ use: InterruptEn/InterruptDis
43 *
44 *****************************************************************************************
45 * @endverbatim
46 */
47
48 /* Exported types ------------------------------------------------------------*/
49
50 /** @defgroup IRQ_Exported_Types IRQ Exported Types
51 * @{
52 */
53 typedef s32 IRQn_Type;
54 typedef void (*HAL_VECTOR_FUN) (void);
55 typedef u32 (*IRQ_FUN)(void *Data);
56 /**
57 * @}
58 */
59
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup IRQ_Exported_Constants IRQ Exported Constants
62 * @{
63 */
64
65 /** @defgroup IRQn_enum
66 * @{
67 */
68 enum IRQn {
69 /****** Cortex-M4 Processor Exceptions Numbers ********/
70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
71 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
72 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
73 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
74 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
75 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
76 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
77 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
78 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
79
80 /****** RTL8710B Specific Interrupt Numbers ************/
81 SYSTEM_ON_IRQ = 0, /*!< 0 SYS Interrupt for wakeup from power save */
82 WDG_IRQ = 1, /*!< 1 Watch dog global insterrupt */
83 RXI300_IRQ = 2, /*!< 2 RXI300 interrupt */
84 UART_LOG_IRQ = 3, /*!< 3 log uart intr */
85 GPIOA_IRQ = 4, /*!< 4 GPIOA portA global interrupt */
86 RTC_IRQ = 5, /*!< 5 rtc timer interrupt */
87 I2C0_IRQ = 6, /*!< 6 I2C0 global interrupt */
88 SPI_FLASH_IRQ = 7, /*!< 7 SPI Flash global interrupt */
89 GPIOB_IRQ = 8, /*!< 8 GPIOB portA global interrupt */
90 UARTLP_IRQ = 9, /*!< 9 UART0 global interrupt */
91 KEYSCAN_IRQ = 10, /*!< 10 KEYSCAN interrupt */
92 CTOUCH_IRQ = 11, /*!< 11 Cap-Touch interrupt */
93 BOR2_IRQ = 12, /*!< 12 BOR2 interrupt */
94 SGPIO_IRQ = 13, /*!< 13 SGPIO interrupt */
95 IPC_IRQ = 14, /*!< 14 IPC_KM0 interrupt */
96 ADC_IRQ = 15, /*!< 15 adc interrupt */
97 QDECODER_IRQ = 16, /*!< 16 Q-DECODER interrupt */
98 TIMER0_IRQ = 17, /*!< 17 Timer0 global interrupt */
99 TIMER1_IRQ = 18, /*!< 18 Timer1 global interrupt */
100 TIMER2_IRQ = 19, /*!< 19 Timer2 global interrupt */
101 TIMER3_IRQ = 20, /*!< 20 Timer3 global interrupt */
102 TIMER4_IRQ = 21, /*!< 21 Timer4 global interrupt */
103 TIMER5_IRQ = 22, /*!< 22 Timer5 global interrupt */
104 LCDC_IRQ = 23, /*!< 23 LCDC interrupt */
105 USB_OTG_IRQ = 24, /*!< 24 USOC interrupt */
106 SDIO_DEVICE_IRQ = 25, /*!< 25 SDIO device global interrupt */
107 SDIO_HOST_IRQ = 26, /*!< 26 SDIO host global interrupt */
108 CRYPTO_IRQ = 27, /*!< 27 IPsec global interrupt */
109 I2S0_PCM0_IRQ = 28, /*!< 28 I2S0 global interrupt */
110 PWR_DOWN_IRQ = 29, /*!< 29 power down enable interrupt */
111 ADC_COMP_IRQ = 30, /*!< 30 ADC compare interrupt */
112 WL_DMA_IRQ = 31, /*!< 31 Wlan Host global interrupt */
113 WL_PROTOCOL_IRQ = 32, /*!< 32 Wlan Firmware Wlan global interrupt */
114 PSRAMC_IRQ = 33, /*!< 33 PSRAM controller interrupt */
115 UART0_IRQ = 34, /*!< 34 UART0 global interrupt */
116 UART1_IRQ = 35, /*!< 35 UART1 BT UART global interrupt */
117 SPI0_IRQ = 36, /*!< 36 SPI0 global interrupt for communication spi */
118 SPI1_IRQ = 37, /*!< 37 SPI1 global interrupt for communication spi */
119 USI_IRQ = 38, /*!< 38 USI global interrupt */
120 IR_IRQ = 39, /*!< 39 IR global interrupt */
121 BT2WL_STS_IRQ = 40, /*!< 40 BT to WL Status Interrupt */
122
123 GDMA0_CHANNEL0_IRQ = 41, /*!< 41 GDMA0 channel 0 global interrupt */
124 GDMA0_CHANNEL1_IRQ = 42, /*!< 42 GDMA0 channel 1 global interrupt */
125 GDMA0_CHANNEL2_IRQ = 43, /*!< 43 GDMA0 channel 2 global interrupt */
126 GDMA0_CHANNEL3_IRQ = 44, /*!< 44 GDMA0 channel 3 global interrupt */
127 GDMA0_CHANNEL4_IRQ = 45, /*!< 45 GDMA0 channel 4 global interrupt */
128 GDMA0_CHANNEL5_IRQ = 46, /*!< 46 GDMA0 channel 5 global interrupt */
129
130 CRYPTO_IRQ_S = 50, /*!< 50 IPsec global interrupt */
131 RXI300_IRQ_S = 51, /*!< 51 RXI300 interrupt */
132 GDMA0_CHANNEL0_IRQ_S = 52, /*!< 52 GDMA0 channel 0 global interrupt */
133 GDMA0_CHANNEL1_IRQ_S = 53, /*!< 53 GDMA0 channel 1 global interrupt */
134 GDMA0_CHANNEL2_IRQ_S = 54, /*!< 54 GDMA0 channel 2 global interrupt */
135 GDMA0_CHANNEL3_IRQ_S = 55, /*!< 55 GDMA0 channel 3 global interrupt */
136 GDMA0_CHANNEL4_IRQ_S = 56, /*!< 56 GDMA0 channel 4 global interrupt */
137 GDMA0_CHANNEL5_IRQ_S = 57, /*!< 57 GDMA0 channel 5 global interrupt */
138 };
139 /**
140 * @}
141 */
142
143 /** @defgroup LPIRQn_enum
144 * @{
145 */
146 enum LPIRQn {
147 /****** Cortex-M4 Processor Exceptions Numbers ********/
148 NonMaskableInt_IRQn_LP = -14, /*!< 2 Non Maskable Interrupt */
149 HardFault_IRQn_LP = -13, /*!< 3 Hard Fault, all classes of Fault */
150 MemoryManagement_IRQn_LP = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
151 BusFault_IRQn_LP = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
152 UsageFault_IRQn_LP = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
153 SVCall_IRQn_LP = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
154 DebugMonitor_IRQn_LP = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
155 PendSV_IRQn_LP = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
156 SysTick_IRQn_LP = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
157
158 /****** RTL8710B Specific Interrupt Numbers ************/
159 SYSTEM_ON_IRQ_LP = 0, /*!< 0 SYS Interrupt for wakeup from power save */
160 WDG_IRQ_LP = 1, /*!< 1 Watch dog global insterrupt */
161 RXI300_IRQ_LP = 2, /*!< 2 RXI300 interrupt */
162 UART_LOG_IRQ_LP = 3, /*!< 3 log uart intr */
163 GPIOA_IRQ_LP = 4, /*!< 4 GPIOA portA global interrupt */
164 RTC_IRQ_LP = 5, /*!< 5 rtc timer interrupt */
165 I2C0_IRQ_LP = 6, /*!< 6 I2C0 global interrupt */
166 SPI_FLASH_IRQ_LP = 7, /*!< 7 SPI Flash global interrupt */
167 GPIOB_IRQ_LP = 8, /*!< 8 GPIOB portA global interrupt */
168 UARTLP_IRQ_LP = 9, /*!< 9 UART0 global interrupt */
169 KEYSCAN_IRQ_LP = 10, /*!< 10 KEYSCAN interrupt */
170 CTOUCH_IRQ_LP = 11, /*!< 11 Cap-Touch interrupt */
171 BOR2_IRQ_LP = 12, /*!< 12 BOR2 interrupt */
172 SGPIO_IRQ_LP = 13, /*!< 13 SGPIO interrupt */
173 IPC_IRQ_LP = 14, /*!< 14 IPC_KM4 interrupt */
174 ADC_IRQ_LP = 15, /*!< 15 adc interrupt */
175 QDECODER_IRQ_LP = 16, /*!< 16 Q-DECODER interrupt */
176 TIMER0_IRQ_LP = 17, /*!< 17 Timer0 global interrupt */
177 TIMER1_IRQ_LP = 18, /*!< 18 Timer1 global interrupt */
178 TIMER2_IRQ_LP = 19, /*!< 19 Timer2 global interrupt */
179 TIMER3_IRQ_LP = 20, /*!< 20 Timer3 global interrupt */
180 TIMER4_IRQ_LP = 21, /*!< 21 Timer4 global interrupt */
181 TIMER5_IRQ_LP = 22, /*!< 22 Timer5 global interrupt */
182 GDMA0_CHANNEL0_IRQ_LP = 23, /*!< 23 GDMA channel 0 global interrupt */
183 GDMA0_CHANNEL1_IRQ_LP = 24, /*!< 24 GDMA channel 1 global interrupt */
184 GDMA0_CHANNEL2_IRQ_LP = 25, /*!< 25 GDMA channel 2 global interrupt */
185 WIFI_FISR_FESR = 26, /*!< 26 WIFI_FISR_FESR interrupt */
186 WIFI_FTSR_MAILBOX = 27, /*!< 27 WIFI_FTSR_MAILBOX interrupt */
187 GDMA0_CHANNEL3_IRQ_LP = 28, /*!< 28 GDMA channel 3 global interrupt */
188 PWR_DOWN_IRQ_LP = 29, /*!< 29 power down enable interrupt */
189 ADC_COMP_IRQ_LP = 30, /*!< 30 ADC compare interrupt */
190 KM4_WAKE_EVENT_IRQ_LP = 31, /*!< 31 KM4 peripherals wakeup CPU event interrupt */
191
192 };
193 /**
194 * @}
195 */
196
197 /**
198 * @}
199 */
200
201 /* Exported functions --------------------------------------------------------*/
202 /** @defgroup IRQ_Exported_Functions IRQ Exported Functions
203 * @{
204 */
205 extern _LONG_CALL_ void irq_table_init(u32 StackP);
206 extern _LONG_CALL_ BOOL irq_register(IRQ_FUN IrqFun, IRQn_Type IrqNum, u32 Data, u32 Priority);
207 extern _LONG_CALL_ BOOL irq_unregister(IRQn_Type IrqNum);
208 extern _LONG_CALL_ void irq_enable(IRQn_Type IrqNum);
209 extern _LONG_CALL_ void irq_disable(IRQn_Type IrqNum);
210
211 #define InterruptRegister irq_register_check
212 #define InterruptUnRegister irq_unregister
213
214 #define InterruptEn(a,b) irq_enable(a)
215 #define InterruptDis(a) irq_disable(a)
216 /**
217 * @}
218 */
219
220 /**
221 * @}
222 */
223
224 /**
225 * @}
226 */
227
228 /* Other Definitions --------------------------------------------------------*/
229 extern IRQ_FUN UserIrqFunTable[];
230 extern u32 UserIrqDataTable[];
231 extern HAL_VECTOR_FUN NewVectorTable[];
232
233 #if defined (ARM_CORE_CM4)
234 #define MAX_VECTOR_TABLE_NUM (64+16)
235 #define MAX_PERIPHERAL_IRQ_NUM 64
236 #define MAX_IRQ_PRIORITY_VALUE 7
237 #define IRQ_PRIORITY_SHIFT 1
238 #else
239 #define MAX_VECTOR_TABLE_NUM (16+32)
240 #define MAX_PERIPHERAL_IRQ_NUM 32
241 #define MAX_IRQ_PRIORITY_VALUE 3
242 #define IRQ_PRIORITY_SHIFT 2
243 #endif
244
245 #define MSP_RAM_LP 0x0008FFFC
246 #define VCT_RAM_LP 0x00080000
247 #define MSP_RAM_HP 0x1007EFFC
248 #define MSP_RAM_HP_NS 0x10004FFC
249
irq_register_check(IRQ_FUN IrqFun,IRQn_Type IrqNum,u32 Data,u32 Priority)250 static inline BOOL irq_register_check(IRQ_FUN IrqFun, IRQn_Type IrqNum, u32 Data, u32 Priority) {
251 if(Priority > MAX_IRQ_PRIORITY_VALUE) {
252 Priority = MAX_IRQ_PRIORITY_VALUE;
253 }
254 Priority = (Priority << IRQ_PRIORITY_SHIFT);
255 return irq_register(IrqFun, IrqNum, Data, Priority);
256 }
257 #endif //_RTL8710B_VECTOR_TABLE_H_
258 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
259