1 /*
2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3 */
4 #ifndef __HAL_DMA_H__
5 #define __HAL_DMA_H__
6
7 #ifdef __cplusplus
8 extern "C" {
9 #endif
10
11 #include "stdint.h"
12 #include "stdbool.h"
13
14 #define HAL_DMA_CHAN_NONE 0xFF
15
16 #define HAL_DMA_MAX_DESC_XFER_SIZE 0xFFF
17
18 enum HAL_DMA_RET_T {
19 HAL_DMA_OK,
20 HAL_DMA_ERR,
21 };
22
23 enum HAL_DMA_GET_CHAN_T {
24 HAL_DMA_HIGH_PRIO,
25 HAL_DMA_LOW_PRIO,
26 HAL_DMA_LOW_PRIO_ONLY
27 };
28
29 // DMA Type of DMA controller
30 enum HAL_DMA_FLOW_CONTROL_T {
31 HAL_DMA_FLOW_M2M_DMA = 0, /* Memory to memory - DMA control */
32 HAL_DMA_FLOW_M2P_DMA = 1, /* Memory to peripheral - DMA control */
33 HAL_DMA_FLOW_P2M_DMA = 2, /* Peripheral to memory - DMA control */
34 HAL_DMA_FLOW_P2P_DMA = 3, /* Source peripheral to destination peripheral - DMA control */
35 HAL_DMA_FLOW_P2P_DSTPERIPH = 4, /* Source peripheral to destination peripheral - destination peripheral control */
36 HAL_DMA_FLOW_M2P_PERIPH = 5, /* Memory to peripheral - peripheral control */
37 HAL_DMA_FLOW_P2M_PERIPH = 6, /* Peripheral to memory - peripheral control */
38 HAL_DMA_FLOW_P2P_SRCPERIPH = 7, /* Source peripheral to destination peripheral - source peripheral control */
39
40 HAL_DMA_FLOW_FLAG_SI = 0x40,
41 HAL_DMA_FLOW_FLAG_DI = 0x80,
42 HAL_DMA_FLOW_FLAG_MASK = (HAL_DMA_FLOW_FLAG_SI | HAL_DMA_FLOW_FLAG_DI),
43
44 HAL_DMA_FLOW_M2P_DI_DMA = HAL_DMA_FLOW_M2P_DMA | HAL_DMA_FLOW_FLAG_DI,
45 HAL_DMA_FLOW_P2M_SI_DMA = HAL_DMA_FLOW_P2M_DMA | HAL_DMA_FLOW_FLAG_SI,
46 HAL_DMA_FLOW_P2P_DI_DMA = HAL_DMA_FLOW_P2P_DMA | HAL_DMA_FLOW_FLAG_DI,
47 HAL_DMA_FLOW_P2P_SI_DMA = HAL_DMA_FLOW_P2P_DMA | HAL_DMA_FLOW_FLAG_SI,
48 };
49
50 // DMA Burst size in Source and Destination definitions
51 enum HAL_DMA_BSIZE_T {
52 HAL_DMA_BSIZE_1 = 0, /* Burst size = 1 */
53 HAL_DMA_BSIZE_4 = 1, /* Burst size = 4 */
54 HAL_DMA_BSIZE_8 = 2, /* Burst size = 8 */
55 HAL_DMA_BSIZE_16 = 3, /* Burst size = 16 */
56 HAL_DMA_BSIZE_32 = 4, /* Burst size = 32 */
57 HAL_DMA_BSIZE_64 = 5, /* Burst size = 64 */
58 HAL_DMA_BSIZE_128 = 6, /* Burst size = 128 */
59 HAL_DMA_BSIZE_256 = 7, /* Burst size = 256 */
60 };
61
62 // Width in Source transfer width and Destination transfer width definitions
63 enum HAL_DMA_WDITH_T {
64 HAL_DMA_WIDTH_BYTE = 0, /* Width = 1 byte */
65 HAL_DMA_WIDTH_HALFWORD = 1, /* Width = 2 bytes */
66 HAL_DMA_WIDTH_WORD = 2, /* Width = 4 bytes */
67 };
68
69 enum HAL_DMA_PERIPH_T {
70 HAL_DMA_PERIPH_NULL = 0,
71 HAL_GPDMA_MEM = 1,
72 HAL_AUDMA_MEM = 2,
73
74 HAL_GPDMA_SDIO = 10,
75 HAL_GPDMA_SDMMC = 11,
76 HAL_GPDMA_I2C0_RX = 12,
77 HAL_GPDMA_I2C0_TX = 13,
78 HAL_GPDMA_SPI_RX = 14,
79 HAL_GPDMA_SPI_TX = 15,
80 HAL_GPDMA_SPILCD_RX = 16,
81 HAL_GPDMA_SPILCD_TX = 17,
82 HAL_GPDMA_UART0_RX = 18,
83 HAL_GPDMA_UART0_TX = 19,
84 HAL_GPDMA_UART1_RX = 20,
85 HAL_GPDMA_UART1_TX = 21,
86 HAL_GPDMA_ISPI_RX = 22,
87 HAL_GPDMA_ISPI_TX = 23,
88 HAL_GPDMA_UART2_RX = 24,
89 HAL_GPDMA_UART2_TX = 25,
90 HAL_GPDMA_FLASH_RX = 26,
91 HAL_GPDMA_FLASH_TX = 27,
92 HAL_GPDMA_I2C1_RX = 28,
93 HAL_GPDMA_I2C1_TX = 29,
94
95 HAL_AUDMA_CODEC_RX = 50,
96 HAL_AUDMA_CODEC_TX = 51,
97 HAL_AUDMA_BTPCM_RX = 52,
98 HAL_AUDMA_BTPCM_TX = 53,
99 HAL_AUDMA_I2S0_RX = 54,
100 HAL_AUDMA_I2S0_TX = 55,
101 HAL_AUDMA_DPD_RX = 56,
102 HAL_AUDMA_DPD_TX = 57,
103 HAL_AUDMA_SPDIF0_RX = 58,
104 HAL_AUDMA_SPDIF0_TX = 59,
105 HAL_AUDMA_SPDIF1_RX = 60,
106 HAL_AUDMA_SPDIF1_TX = 61,
107 HAL_AUDMA_DSD_RX = 62,
108 HAL_AUDMA_DSD_TX = 63,
109 HAL_AUDMA_MC_RX = 64,
110 HAL_AUDMA_FFT_RX = 65,
111 HAL_AUDMA_FFT_TX = 66,
112 HAL_AUDMA_FIR_RX = 67,
113 HAL_AUDMA_FIR_TX = 68,
114 HAL_AUDMA_IIR_RX = 69,
115 HAL_AUDMA_IIR_TX = 70,
116 HAL_AUDMA_BTDUMP = 71,
117 HAL_AUDMA_I2S1_RX = 72,
118 HAL_AUDMA_I2S1_TX = 73,
119 HAL_AUDMA_FM_RX = 74,
120 HAL_AUDMA_FMDUMP0 = 75,
121 HAL_AUDMA_FMDUMP1 = 76,
122 HAL_AUDMA_CODEC_TX2 = 77,
123
124 HAL_DMA_PERIPH_QTY,
125 };
126
127 struct HAL_DMA_DESC_T;
128
129 typedef void (*HAL_DMA_IRQ_HANDLER_T)(uint8_t chan, uint32_t remain_tsize, uint32_t error, struct HAL_DMA_DESC_T *lli);
130
131 typedef void (*HAL_DMA_START_CALLBACK_T)(uint8_t chan);
132
133 typedef void (*HAL_DMA_DELAY_FUNC)(uint32_t ms);
134
135 // DMA structure using for DMA configuration
136 struct HAL_DMA_CH_CFG_T {
137 uint8_t ch; /* DMA channel number */
138 uint8_t try_burst;
139 uint16_t src_tsize; /* Length/Size of transfer */
140 enum HAL_DMA_WDITH_T src_width;
141 enum HAL_DMA_WDITH_T dst_width;
142 enum HAL_DMA_BSIZE_T src_bsize;
143 enum HAL_DMA_BSIZE_T dst_bsize;
144 enum HAL_DMA_FLOW_CONTROL_T type; /* Transfer Type */
145 enum HAL_DMA_PERIPH_T src_periph;
146 enum HAL_DMA_PERIPH_T dst_periph;
147 uint32_t src; /* Physical Source Address */
148 uint32_t dst; /* Physical Destination Address */
149 HAL_DMA_IRQ_HANDLER_T handler;
150 HAL_DMA_START_CALLBACK_T start_cb;
151 };
152
153 // Transfer Descriptor structure typedef
154 struct HAL_DMA_DESC_T {
155 uint32_t src; /* Source address */
156 uint32_t dst; /* Destination address */
157 uint32_t lli; /* Pointer to next descriptor structure */
158 uint32_t ctrl; /* Control word that has transfer size, type etc. */
159 };
160
161 // DMA 2D configuration structure
162 struct HAL_DMA_2D_CFG_T {
163 int16_t xmodify;
164 uint16_t xcount;
165 int16_t ymodify;
166 uint16_t ycount;
167 };
168
169 //=============================================================
170
171 #if (CHIP_HAS_DMA != 0)
172 void hal_dma_open(void);
173
174 void hal_dma_close(void);
175
176 bool hal_dma_chan_busy(uint8_t ch);
177
178 uint8_t hal_dma_get_chan(enum HAL_DMA_PERIPH_T periph, enum HAL_DMA_GET_CHAN_T policy);
179
180 void hal_dma_free_chan(uint8_t ch);
181
182 uint32_t hal_dma_cancel(uint8_t ch);
183
184 uint32_t hal_dma_stop(uint8_t ch);
185
186 enum HAL_DMA_RET_T hal_dma_init_desc(struct HAL_DMA_DESC_T *desc,
187 const struct HAL_DMA_CH_CFG_T *cfg,
188 const struct HAL_DMA_DESC_T *next,
189 int tc_irq);
190
191 enum HAL_DMA_RET_T hal_dma_sg_start(const struct HAL_DMA_DESC_T *desc,
192 const struct HAL_DMA_CH_CFG_T *cfg);
193
194 enum HAL_DMA_RET_T hal_dma_sg_2d_start(const struct HAL_DMA_DESC_T *desc,
195 const struct HAL_DMA_CH_CFG_T *cfg,
196 const struct HAL_DMA_2D_CFG_T *src_2d,
197 const struct HAL_DMA_2D_CFG_T *dst_2d);
198
199 enum HAL_DMA_RET_T hal_dma_start(const struct HAL_DMA_CH_CFG_T *cfg);
200
201 uint32_t hal_dma_get_cur_src_addr(uint8_t ch);
202
203 uint32_t hal_dma_get_cur_dst_addr(uint8_t ch);
204
205 uint32_t hal_dma_get_sg_remain_size(uint8_t ch);
206
207 enum HAL_DMA_RET_T hal_dma_irq_run_chan(uint8_t ch);
208
209 bool hal_dma_busy(void);
210
211 HAL_DMA_DELAY_FUNC hal_dma_set_delay_func(HAL_DMA_DELAY_FUNC new_func);
212
213 void hal_dma_remap_periph(enum HAL_DMA_PERIPH_T periph, int enable);
214
215 void hal_dma_tc_irq_enable(uint8_t ch);
216
217 void hal_dma_tc_irq_disable(uint8_t ch);
218 #else /*CHIP_HAS_DMA != 0*/
hal_dma_open(void)219 static inline void hal_dma_open(void) {}
220
hal_dma_close(void)221 static inline void hal_dma_close(void) {}
222
hal_dma_chan_busy(uint8_t ch)223 static inline bool hal_dma_chan_busy(uint8_t ch) {return true;}
224
hal_dma_get_chan(enum HAL_DMA_PERIPH_T periph,enum HAL_DMA_GET_CHAN_T policy)225 static inline uint8_t hal_dma_get_chan(enum HAL_DMA_PERIPH_T periph, enum HAL_DMA_GET_CHAN_T policy) {return HAL_DMA_CHAN_NONE;}
226
hal_dma_free_chan(uint8_t ch)227 static inline void hal_dma_free_chan(uint8_t ch) {}
228
hal_dma_cancel(uint8_t ch)229 static inline uint32_t hal_dma_cancel(uint8_t ch) {return 0;}
230
hal_dma_stop(uint8_t ch)231 static inline uint32_t hal_dma_stop(uint8_t ch) {return 0;}
232
hal_dma_init_desc(struct HAL_DMA_DESC_T * desc,const struct HAL_DMA_CH_CFG_T * cfg,const struct HAL_DMA_DESC_T * next,int tc_irq)233 static inline enum HAL_DMA_RET_T hal_dma_init_desc(struct HAL_DMA_DESC_T *desc,
234 const struct HAL_DMA_CH_CFG_T *cfg,
235 const struct HAL_DMA_DESC_T *next,
236 int tc_irq) {return HAL_DMA_ERR;}
237
hal_dma_sg_start(const struct HAL_DMA_DESC_T * desc,const struct HAL_DMA_CH_CFG_T * cfg)238 static inline enum HAL_DMA_RET_T hal_dma_sg_start(const struct HAL_DMA_DESC_T *desc,
239 const struct HAL_DMA_CH_CFG_T *cfg) {return HAL_DMA_ERR;}
240
hal_dma_sg_2d_start(const struct HAL_DMA_DESC_T * desc,const struct HAL_DMA_CH_CFG_T * cfg,const struct HAL_DMA_2D_CFG_T * src_2d,const struct HAL_DMA_2D_CFG_T * dst_2d)241 static inline enum HAL_DMA_RET_T hal_dma_sg_2d_start(const struct HAL_DMA_DESC_T *desc,
242 const struct HAL_DMA_CH_CFG_T *cfg,
243 const struct HAL_DMA_2D_CFG_T *src_2d,
244 const struct HAL_DMA_2D_CFG_T *dst_2d) {return HAL_DMA_ERR;}
245
hal_dma_start(const struct HAL_DMA_CH_CFG_T * cfg)246 static inline enum HAL_DMA_RET_T hal_dma_start(const struct HAL_DMA_CH_CFG_T *cfg) {return HAL_DMA_ERR;}
247
hal_dma_get_cur_src_addr(uint8_t ch)248 static inline uint32_t hal_dma_get_cur_src_addr(uint8_t ch) {return 0;}
249
hal_dma_get_cur_dst_addr(uint8_t ch)250 static inline uint32_t hal_dma_get_cur_dst_addr(uint8_t ch) {return 0;}
251
hal_dma_get_sg_remain_size(uint8_t ch)252 static inline uint32_t hal_dma_get_sg_remain_size(uint8_t ch) {return 0;}
253
hal_dma_irq_run_chan(uint8_t ch)254 static inline enum HAL_DMA_RET_T hal_dma_irq_run_chan(uint8_t ch) {return HAL_DMA_ERR;}
255
hal_dma_busy(void)256 static inline bool hal_dma_busy(void) {return true;}
257
hal_dma_set_delay_func(HAL_DMA_DELAY_FUNC new_func)258 static inline HAL_DMA_DELAY_FUNC hal_dma_set_delay_func(HAL_DMA_DELAY_FUNC new_func) {return (HAL_DMA_DELAY_FUNC)0;}
259
hal_dma_remap_periph(enum HAL_DMA_PERIPH_T periph,int enable)260 static inline void hal_dma_remap_periph(enum HAL_DMA_PERIPH_T periph, int enable) {}
261
hal_dma_tc_irq_enable(uint8_t ch)262 static inline void hal_dma_tc_irq_enable(uint8_t ch) {}
263
hal_dma_tc_irq_disable(uint8_t ch)264 static inline void hal_dma_tc_irq_disable(uint8_t ch) {}
265 #endif /*CHIP_HAS_DMA != 0*/
266 //=============================================================
267
268 #define hal_audma_open hal_dma_open
269 #define hal_audma_close hal_dma_close
270 #define hal_audma_chan_busy hal_dma_chan_busy
271 #define hal_audma_get_chan hal_dma_get_chan
272 #define hal_audma_free_chan hal_dma_free_chan
273 #define hal_audma_cancel hal_dma_cancel
274 #define hal_audma_stop hal_dma_stop
275 #define hal_audma_init_desc hal_dma_init_desc
276 #define hal_audma_sg_start hal_dma_sg_start
277 #define hal_audma_start hal_dma_start
278 #define hal_audma_get_cur_src_addr hal_dma_get_cur_src_addr
279 #define hal_audma_get_cur_dst_addr hal_dma_get_cur_dst_addr
280 #define hal_audma_get_sg_remain_size hal_dma_get_sg_remain_size
281 #define hal_audma_irq_run_chan hal_dma_irq_run_chan
282
283 #define hal_gpdma_open hal_dma_open
284 #define hal_gpdma_close hal_dma_close
285 #define hal_gpdma_chan_busy hal_dma_chan_busy
286 #define hal_gpdma_get_chan hal_dma_get_chan
287 #define hal_gpdma_free_chan hal_dma_free_chan
288 #define hal_gpdma_cancel hal_dma_cancel
289 #define hal_gpdma_stop hal_dma_stop
290 #define hal_gpdma_init_desc hal_dma_init_desc
291 #define hal_gpdma_sg_start hal_dma_sg_start
292 #define hal_gpdma_start hal_dma_start
293 #define hal_gpdma_get_cur_src_addr hal_dma_get_cur_src_addr
294 #define hal_gpdma_get_cur_dst_addr hal_dma_get_cur_dst_addr
295 #define hal_gpdma_get_sg_remain_size hal_dma_get_sg_remain_size
296 #define hal_gpdma_irq_run_chan hal_dma_irq_run_chan
297
298 //=============================================================
299
300 #ifdef __cplusplus
301 }
302 #endif
303
304 #endif
305