1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef __HAL_CMU_H__ 5 #define __HAL_CMU_H__ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #include "stdint.h" 12 #include "plat_addr_map.h" 13 #include CHIP_SPECIFIC_HDR(hal_cmu) 14 15 #ifndef HAL_CMU_DEFAULT_CRYSTAL_FREQ 16 #define HAL_CMU_DEFAULT_CRYSTAL_FREQ 26000000 17 #endif 18 19 #define LPU_TIMER_US(us) (((us) * 32 + 1000 - 1) / 1000) 20 21 enum HAL_CMU_CLK_STATUS_T { 22 HAL_CMU_CLK_DISABLED, 23 HAL_CMU_CLK_ENABLED, 24 }; 25 26 enum HAL_CMU_CLK_MODE_T { 27 HAL_CMU_CLK_AUTO, 28 HAL_CMU_CLK_MANUAL, 29 }; 30 31 enum HAL_CMU_RST_STATUS_T { 32 HAL_CMU_RST_SET, 33 HAL_CMU_RST_CLR, 34 }; 35 36 enum HAL_CMU_TIMER_ID_T { 37 HAL_CMU_TIMER_ID_00, 38 HAL_CMU_TIMER_ID_01, 39 HAL_CMU_TIMER_ID_10, 40 HAL_CMU_TIMER_ID_11, 41 HAL_CMU_TIMER_ID_20, 42 HAL_CMU_TIMER_ID_21, 43 }; 44 45 #ifndef HAL_CMU_FREQ_T 46 enum HAL_CMU_FREQ_T { 47 HAL_CMU_FREQ_32K, 48 HAL_CMU_FREQ_26M, 49 HAL_CMU_FREQ_52M, 50 HAL_CMU_FREQ_78M, 51 HAL_CMU_FREQ_104M, 52 HAL_CMU_FREQ_208M, 53 54 HAL_CMU_FREQ_QTY 55 }; 56 #endif 57 58 #ifndef HAL_CMU_PLL_T 59 enum HAL_CMU_PLL_T { 60 HAL_CMU_PLL_AUD, 61 HAL_CMU_PLL_USB, 62 63 HAL_CMU_PLL_QTY 64 }; 65 #endif 66 67 #ifndef HAL_CMU_PLL_USER_T 68 enum HAL_CMU_PLL_USER_T { 69 HAL_CMU_PLL_USER_SYS, 70 HAL_CMU_PLL_USER_AUD, 71 HAL_CMU_PLL_USER_USB, 72 73 HAL_CMU_PLL_USER_QTY, 74 HAL_CMU_PLL_USER_ALL = HAL_CMU_PLL_USER_QTY, 75 }; 76 #endif 77 78 enum HAL_CMU_PERIPH_FREQ_T { 79 HAL_CMU_PERIPH_FREQ_26M, 80 HAL_CMU_PERIPH_FREQ_52M, 81 82 HAL_CMU_PERIPH_FREQ_QTY 83 }; 84 85 enum HAL_CMU_LPU_CLK_CFG_T { 86 HAL_CMU_LPU_CLK_NONE, 87 HAL_CMU_LPU_CLK_26M, 88 HAL_CMU_LPU_CLK_PLL, 89 90 HAL_CMU_LPU_CLK_QTY 91 }; 92 93 enum HAL_CMU_LPU_SLEEP_MODE_T { 94 HAL_CMU_LPU_SLEEP_MODE_SYS, 95 HAL_CMU_LPU_SLEEP_MODE_CHIP, 96 97 HAL_CMU_LPU_SLEEP_MODE_QTY 98 }; 99 100 #ifndef HAL_PWM_ID_T 101 enum HAL_PWM_ID_T { 102 HAL_PWM_ID_0, 103 HAL_PWM_ID_1, 104 HAL_PWM_ID_2, 105 HAL_PWM_ID_3, 106 107 HAL_PWM_ID_QTY 108 }; 109 #endif 110 111 #ifndef HAL_I2S_ID_T 112 enum HAL_I2S_ID_T { 113 HAL_I2S_ID_0 = 0, 114 115 HAL_I2S_ID_QTY, 116 }; 117 #endif 118 119 #ifndef HAL_SPDIF_ID_T 120 enum HAL_SPDIF_ID_T { 121 HAL_SPDIF_ID_0 = 0, 122 123 HAL_SPDIF_ID_QTY, 124 }; 125 #endif 126 127 enum HAL_CMU_USB_CLOCK_SEL_T { 128 HAL_CMU_USB_CLOCK_SEL_PLL, 129 HAL_CMU_USB_CLOCK_SEL_24M_X2, 130 HAL_CMU_USB_CLOCK_SEL_48M, 131 HAL_CMU_USB_CLOCK_SEL_26M_X2, 132 HAL_CMU_USB_CLOCK_SEL_26M_X4, 133 }; 134 135 void hal_cmu_set_crystal_freq_index(uint32_t index); 136 137 uint32_t hal_cmu_get_crystal_freq(void); 138 139 uint32_t hal_cmu_get_default_crystal_freq(void); 140 141 int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id); 142 143 int hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id); 144 145 enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id); 146 147 int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mode); 148 149 enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id); 150 151 int hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id); 152 153 int hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id); 154 155 enum HAL_CMU_RST_STATUS_T hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id); 156 157 int hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id); 158 159 int hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id, uint32_t div); 160 161 void hal_cmu_timer0_select_fast(void); 162 163 void hal_cmu_timer0_select_slow(void); 164 165 void hal_cmu_timer1_select_fast(void); 166 167 void hal_cmu_timer1_select_slow(void); 168 169 void hal_cmu_timer2_select_fast(void); 170 171 void hal_cmu_timer2_select_slow(void); 172 173 void hal_cmu_dsp_timer0_select_fast(void); 174 175 void hal_cmu_dsp_timer0_select_slow(void); 176 177 void hal_cmu_dsp_timer1_select_fast(void); 178 179 void hal_cmu_dsp_timer1_select_slow(void); 180 181 int hal_cmu_periph_set_div(uint32_t div); 182 183 int hal_cmu_uart0_set_div(uint32_t div); 184 185 int hal_cmu_uart1_set_div(uint32_t div); 186 187 int hal_cmu_uart2_set_div(uint32_t div); 188 189 int hal_cmu_spi_set_div(uint32_t div); 190 191 int hal_cmu_slcd_set_div(uint32_t div); 192 193 int hal_cmu_sdio_set_div(uint32_t div); 194 195 int hal_cmu_sdmmc_set_div(uint32_t div); 196 197 int hal_cmu_i2c_set_div(uint32_t div); 198 199 int hal_cmu_uart0_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 200 201 int hal_cmu_uart1_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 202 203 int hal_cmu_uart2_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 204 205 int hal_cmu_spi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 206 207 int hal_cmu_slcd_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 208 209 int hal_cmu_sdio_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 210 211 int hal_cmu_sdmmc_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 212 213 int hal_cmu_i2c_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 214 215 int hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 216 217 int hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id, uint32_t freq); 218 219 int hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq); 220 221 int hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq); 222 223 int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq); 224 225 enum HAL_CMU_FREQ_T hal_cmu_sys_get_freq(void); 226 227 enum HAL_CMU_FREQ_T hal_cmu_flash_get_freq(void); 228 229 int hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll); 230 231 int hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll); 232 233 int hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll); 234 235 int hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll); 236 237 int hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user); 238 239 int hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user); 240 241 void hal_cmu_audio_resample_enable(void); 242 243 void hal_cmu_audio_resample_disable(void); 244 245 int hal_cmu_get_audio_resample_status(void); 246 247 int hal_cmu_codec_adc_set_div(uint32_t div); 248 249 uint32_t hal_cmu_codec_adc_get_div(void); 250 251 int hal_cmu_codec_dac_set_div(uint32_t div); 252 253 uint32_t hal_cmu_codec_dac_get_div(void); 254 255 void hal_cmu_codec_clock_enable(void); 256 257 void hal_cmu_codec_clock_disable(void); 258 259 void hal_cmu_codec_reset_set(void); 260 261 void hal_cmu_codec_reset_clear(void); 262 263 void hal_cmu_codec_iir_enable(uint32_t speed); 264 265 void hal_cmu_codec_iir_disable(void); 266 267 int hal_cmu_codec_iir_set_div(uint32_t div); 268 269 void hal_cmu_codec_fir_enable(uint32_t speed); 270 271 void hal_cmu_codec_fir_disable(void); 272 273 int hal_cmu_codec_fir_set_div(uint32_t div); 274 275 void hal_cmu_codec_rs_enable(uint32_t speed); 276 277 void hal_cmu_codec_rs_disable(void); 278 279 int hal_cmu_codec_rs_set_div(uint32_t div); 280 281 void hal_cmu_codec_set_fault_mask(uint32_t msk); 282 283 void hal_cmu_i2s_clock_out_enable(enum HAL_I2S_ID_T id); 284 285 void hal_cmu_i2s_clock_out_disable(enum HAL_I2S_ID_T id); 286 287 void hal_cmu_i2s_set_slave_mode(enum HAL_I2S_ID_T id); 288 289 void hal_cmu_i2s_set_master_mode(enum HAL_I2S_ID_T id); 290 291 void hal_cmu_i2s_clock_enable(enum HAL_I2S_ID_T id); 292 293 void hal_cmu_i2s_clock_disable(enum HAL_I2S_ID_T id); 294 295 int hal_cmu_i2s_set_div(enum HAL_I2S_ID_T id, uint32_t div); 296 297 int hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id); 298 299 void hal_cmu_i2s_mclk_disable(void); 300 301 void hal_cmu_pcm_clock_out_enable(void); 302 303 void hal_cmu_pcm_clock_out_disable(void); 304 305 void hal_cmu_pcm_set_slave_mode(int clk_pol); 306 307 void hal_cmu_pcm_set_master_mode(void); 308 309 void hal_cmu_pcm_clock_enable(void); 310 311 void hal_cmu_pcm_clock_disable(void); 312 313 int hal_cmu_pcm_set_div(uint32_t div); 314 315 int hal_cmu_spdif_clock_enable(enum HAL_SPDIF_ID_T id); 316 317 int hal_cmu_spdif_clock_disable(enum HAL_SPDIF_ID_T id); 318 319 int hal_cmu_spdif_set_div(enum HAL_SPDIF_ID_T id, uint32_t div); 320 321 void hal_cmu_usb_set_device_mode(void); 322 323 void hal_cmu_usb_set_host_mode(void); 324 325 void hal_cmu_rom_select_usb_clock(enum HAL_CMU_USB_CLOCK_SEL_T sel); 326 327 void hal_cmu_usb_clock_enable(void); 328 329 void hal_cmu_usb_clock_disable(void); 330 331 void hal_cmu_bt_clock_enable(void); 332 333 void hal_cmu_bt_clock_disable(void); 334 335 void hal_cmu_bt_reset_set(void); 336 337 void hal_cmu_bt_reset_clear(void); 338 void hal_cmu_bt_module_reset_clear(void); 339 340 void hal_cmu_bt_module_init(void); 341 342 int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id); 343 344 void hal_cmu_clock_out_disable(void); 345 346 void hal_cmu_write_lock(void); 347 348 void hal_cmu_write_unlock(void); 349 350 void hal_cmu_sys_reboot(void); 351 352 void hal_cmu_jtag_enable(void); 353 354 void hal_cmu_jtag_disable(void); 355 356 void hal_cmu_jtag_clock_enable(void); 357 358 void hal_cmu_jtag_clock_disable(void); 359 360 void hal_cmu_simu_init(void); 361 362 void hal_cmu_simu_pass(void); 363 364 void hal_cmu_simu_fail(void); 365 366 void hal_cmu_misc_init(void); 367 368 void hal_cmu_misc_pass(void); 369 370 void hal_cmu_misc_fail(void); 371 372 void hal_cmu_simu_tag(uint8_t shift); 373 374 void hal_cmu_simu_clr_tag(uint8_t shift); 375 376 void hal_cmu_simu_set_val(uint32_t val); 377 378 uint32_t hal_cmu_simu_get_val(void); 379 380 void hal_cmu_low_freq_mode_init(void); 381 382 void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq); 383 384 void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq); 385 386 void hal_cmu_rom_enable_pll(void); 387 388 void hal_cmu_programmer_enable_pll(void); 389 390 void hal_cmu_init_pll_selection(void); 391 392 void hal_cmu_rom_setup(void); 393 394 void hal_cmu_fpga_setup(void); 395 396 void hal_cmu_setup(void); 397 398 // Some internal functions 399 400 void hal_cmu_apb_init_div(void); 401 402 void hal_cmu_rom_clock_init(void); 403 404 void hal_cmu_init_chip_feature(uint16_t feature); 405 406 void hal_cmu_osc_x2_enable(void); 407 408 void hal_cmu_osc_x4_enable(void); 409 410 void hal_cmu_module_init_state(void); 411 412 void hal_cmu_ema_init(void); 413 414 void hal_cmu_lpu_wait_26m_ready(void); 415 416 int hal_cmu_lpu_busy(void); 417 418 int hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg); 419 420 int hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode); 421 422 void hal_cmu_set_wakeup_pc(uint32_t pc); 423 424 volatile uint32_t *hal_cmu_get_bootmode_addr(void); 425 426 volatile uint32_t *hal_cmu_get_memsc_addr(void); 427 428 #ifdef __cplusplus 429 } 430 #endif 431 432 #endif 433 434