1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef NORFLASH_HAL_H 5 #define NORFLASH_HAL_H 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #include "plat_types.h" 12 #include "hal_cmu.h" 13 14 #define HAL_NORFLASH_DEVICE_ID_LEN 3 15 16 #define HAL_NORFLASH_UNIQUE_ID_LEN 16 17 #define FLASH_SECTOR_SIZE_IN_BYTES 4096 18 #define FLASH_BLOCK_SIZE_IN_BYTES (32*1024) 19 20 enum HAL_NORFLASH_ID_T { 21 HAL_NORFLASH_ID_0 = 0, 22 HAL_NORFLASH_ID_NUM, 23 }; 24 25 enum HAL_NORFLASH_RET_T { 26 HAL_NORFLASH_OK, 27 HAL_NORFLASH_SUSPENDED, 28 HAL_NORFLASH_ERR, 29 HAL_NORFLASH_BAD_ID, 30 HAL_NORFLASH_BAD_DIV, 31 HAL_NORFLASH_BAD_DIV_VERIF, 32 HAL_NORFLASH_BAD_CFG, 33 HAL_NORFLASH_BAD_OP, 34 HAL_NORFLASH_BAD_CALIB, 35 HAL_NORFLASH_BAD_ADDR, 36 HAL_NORFLASH_BAD_LEN, 37 HAL_NORFLASH_NOT_OPENED, 38 }; 39 40 enum HAL_NORFLASH_SPEED { 41 HAL_NORFLASH_SPEED_13M = 13000000, 42 HAL_NORFLASH_SPEED_26M = 26000000, 43 HAL_NORFLASH_SPEED_52M = 52000000, 44 HAL_NORFLASH_SPEED_78M = 78000000, 45 HAL_NORFLASH_SPEED_104M = 104000000, 46 HAL_NORFLASH_SPEED_130M = 130000000, 47 HAL_NORFLASH_SPEED_156M = 156000000, 48 HAL_NORFLASH_SPEED_182M = 182000000, 49 HAL_NORFLASH_SPEED_208M = 208000000, 50 HAL_NORFLASH_SPEED_234M = 234000000, 51 }; 52 53 enum HAL_NORFLASH_OP_MODE { 54 // Different groups can be used together, different flash-device may support different option(s) 55 56 // (1) basic read mode 57 /* standard spi mode */ 58 HAL_NORFLASH_OP_MODE_STAND_SPI = 0x1, 59 /* fast spi mode*/ 60 HAL_NORFLASH_OP_MODE_FAST_SPI = 0x2, 61 /* dual mode */ 62 HAL_NORFLASH_OP_MODE_DUAL_OUTPUT = 0x4, 63 /* dual mode */ 64 HAL_NORFLASH_OP_MODE_DUAL_IO = 0x8, 65 /* quad mode */ 66 HAL_NORFLASH_OP_MODE_QUAD_OUTPUT = 0x10, 67 /* quad mode */ 68 HAL_NORFLASH_OP_MODE_QUAD_IO = 0x20, 69 70 // (2) extend read mode 71 // read accelerate (no cmd bettween read operation) : 72 // may need Dual or Quad Mode 73 HAL_NORFLASH_OP_MODE_CONTINUOUS_READ = 0x40, 74 // read high performance mode 75 HAL_NORFLASH_OP_MODE_HIGH_PERFORMANCE = 0x80, 76 // read wrap mode 77 HAL_NORFLASH_OP_MODE_READ_WRAP = 0x100, 78 79 // (3) program mode. 80 // page program mode 81 HAL_NORFLASH_OP_MODE_PAGE_PROGRAM = 0x200, 82 // dual program mode 83 HAL_NORFLASH_OP_MODE_DUAL_PAGE_PROGRAM = 0x400, 84 // quad program mode 85 HAL_NORFLASH_OP_MODE_QUAD_PAGE_PROGRAM = 0x800, 86 87 // (4) advanced features 88 // suspend and resume 89 HAL_NORFLASH_OP_MODE_SUSPEND = 0x1000, 90 // erase in standard spi mode 91 HAL_NORFLASH_OP_MODE_ERASE_IN_STD = 0x2000, 92 93 HAL_NORFLASH_OP_MODE_RESERVED = 0xFFFFFFFF, 94 }; 95 96 struct HAL_NORFLASH_CONFIG_T { 97 uint32_t source_clk; 98 uint32_t speed; 99 enum HAL_NORFLASH_OP_MODE mode; 100 101 /* internal use : can be config if need to (useful for rom) */ 102 uint8_t override_config:1; 103 uint8_t neg_phase:1; 104 uint8_t pos_neg:1; 105 uint8_t cmdquad:1; 106 uint8_t samdly:3; 107 uint8_t div; /* least 2 */ 108 uint8_t dualmode:1; 109 uint8_t holdpin:1; 110 uint8_t wprpin:1; 111 uint8_t quadmode:1; 112 113 uint8_t spiruen:3; 114 uint8_t spirden:3; 115 116 uint8_t dualiocmd; 117 uint8_t rdcmd; 118 uint8_t frdcmd; 119 uint8_t qrdcmd; /* quad io cmd */ 120 #if defined(CHIP_BEST1400) || defined(CHIP_BEST1402) 121 uint8_t dec_enable; /* 1: enable decoder, 0: disable decoder */ 122 uint8_t dec_idx; /* decoder key index ,from 0 to 3 */ 123 uint32_t dec_addr; /* start address where to decode */ 124 uint32_t dec_size; /* bytes number will be decoded */ 125 #endif 126 }; 127 128 /* hal api */ 129 void hal_norflash_set_freq(enum HAL_CMU_FREQ_T freq); 130 enum HAL_NORFLASH_RET_T hal_norflash_init(void); 131 enum HAL_NORFLASH_RET_T hal_norflash_deinit(void); 132 enum HAL_NORFLASH_RET_T hal_norflash_open(enum HAL_NORFLASH_ID_T id, const struct HAL_NORFLASH_CONFIG_T *cfg); 133 enum HAL_CMU_FREQ_T hal_norflash_clk_to_cmu_freq(uint32_t clk); 134 enum HAL_NORFLASH_RET_T hal_norflash_get_size(enum HAL_NORFLASH_ID_T id, uint32_t *total_size, uint32_t *block_size, uint32_t *sector_size, uint32_t *page_size); 135 enum HAL_NORFLASH_RET_T hal_norflash_get_boundary(enum HAL_NORFLASH_ID_T id, uint32_t address, uint32_t* block_boundary, uint32_t* sector_boundary); 136 enum HAL_NORFLASH_RET_T hal_norflash_get_id(enum HAL_NORFLASH_ID_T id, uint8_t *value, uint32_t len); 137 enum HAL_NORFLASH_RET_T hal_norflash_get_unique_id(enum HAL_NORFLASH_ID_T id, uint8_t *value, uint32_t len); 138 enum HAL_NORFLASH_RET_T hal_norflash_enable_protection(enum HAL_NORFLASH_ID_T id); 139 enum HAL_NORFLASH_RET_T hal_norflash_disable_protection(enum HAL_NORFLASH_ID_T id); 140 enum HAL_NORFLASH_RET_T hal_norflash_erase_chip(enum HAL_NORFLASH_ID_T id); 141 enum HAL_NORFLASH_RET_T hal_norflash_erase_suspend(enum HAL_NORFLASH_ID_T id, uint32_t start_address, uint32_t len, int suspend); 142 enum HAL_NORFLASH_RET_T hal_norflash_erase(enum HAL_NORFLASH_ID_T id, uint32_t start_address, uint32_t len); 143 enum HAL_NORFLASH_RET_T hal_norflash_erase_resume(enum HAL_NORFLASH_ID_T id, int suspend); 144 enum HAL_NORFLASH_RET_T hal_norflash_write_suspend(enum HAL_NORFLASH_ID_T id, uint32_t start_address, const uint8_t *buffer, uint32_t len, int suspend); 145 enum HAL_NORFLASH_RET_T hal_norflash_write(enum HAL_NORFLASH_ID_T id, uint32_t start_address, const uint8_t *buffer, uint32_t len); 146 enum HAL_NORFLASH_RET_T hal_norflash_write_resume(enum HAL_NORFLASH_ID_T id, int suspend); 147 enum HAL_NORFLASH_RET_T hal_norflash_suspend_check_irq(enum HAL_NORFLASH_ID_T id, uint32_t irq_num); 148 enum HAL_NORFLASH_RET_T hal_norflash_read(enum HAL_NORFLASH_ID_T id, uint32_t start_address, uint8_t *buffer, uint32_t len); 149 enum HAL_NORFLASH_RET_T hal_norflash_close(enum HAL_NORFLASH_ID_T id); 150 void hal_norflash_sleep(enum HAL_NORFLASH_ID_T id); 151 void hal_norflash_wakeup(enum HAL_NORFLASH_ID_T id); 152 int hal_norflash_busy(void); 153 uint32_t hal_norflash_get_flash_total_size(enum HAL_NORFLASH_ID_T id); 154 int hal_norflash_opened(enum HAL_NORFLASH_ID_T id); 155 enum HAL_NORFLASH_RET_T hal_norflash_get_open_state(enum HAL_NORFLASH_ID_T id); 156 enum HAL_NORFLASH_RET_T hal_norflash_security_register_lock(enum HAL_NORFLASH_ID_T id, uint32_t start_address, uint32_t len); 157 enum HAL_NORFLASH_RET_T hal_norflash_security_register_erase(enum HAL_NORFLASH_ID_T id, uint32_t start_address, uint32_t len); 158 enum HAL_NORFLASH_RET_T hal_norflash_security_register_write(enum HAL_NORFLASH_ID_T id, uint32_t start_address, const uint8_t *buffer, uint32_t len); 159 enum HAL_NORFLASH_RET_T hal_norflash_security_register_read(enum HAL_NORFLASH_ID_T id, uint32_t start_address, uint8_t *buffer, uint32_t len); 160 enum HAL_NORFLASH_RET_T hal_norflash_enable_remap(enum HAL_NORFLASH_ID_T id, uint32_t addr, uint32_t len, uint32_t offset); 161 enum HAL_NORFLASH_RET_T hal_norflash_disable_remap(enum HAL_NORFLASH_ID_T id); 162 enum HAL_NORFLASH_RET_T hal_norflash_re_enable_remap(enum HAL_NORFLASH_ID_T id); 163 int hal_norflash_get_remap_status(enum HAL_NORFLASH_ID_T id); 164 165 #ifdef __cplusplus 166 } 167 #endif 168 169 #endif /* NORFLASH_HAL_H */ 170