1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __REG_I2SIP_H_
5 #define __REG_I2SIP_H_
6 
7 #include "plat_types.h"
8 
9 #define I2SIP_FIFO_DEPTH 8
10 #define I2SIP_CHAN_REG_SIZE 0x40
11 #define I2SIP_CHAN_REG(c, r) (c * I2SIP_CHAN_REG_SIZE + r)
12 
13 /* i2sip register */
14 /* enable register */
15 #define I2SIP_ENABLE_REG_REG_OFFSET 0x0
16 #define I2SIP_ENABLE_REG_I2S_ENABLE_SHIFT (0)
17 #define I2SIP_ENABLE_REG_I2S_ENABLE_MASK ((0x1)<<I2SIP_ENABLE_REG_I2S_ENABLE_SHIFT)
18 #ifndef CHIP_BEST1000
19 #define I2SIP_ENABLE_REG_SLAVE_MODE_SHIFT (1)
20 #define I2SIP_ENABLE_REG_SLAVE_MODE_MASK (1 << I2SIP_ENABLE_REG_SLAVE_MODE_SHIFT)
21 #endif
22 #define I2SIP_ENABLE_REG_SPDIF_ENABLE_SHIFT (8)
23 #define I2SIP_ENABLE_REG_SPDIF_ENABLE_MASK ((0x1)<<I2SIP_ENABLE_REG_SPDIF_ENABLE_SHIFT)
24 
25 /* recv block enable register */
26 #define I2SIP_RX_BLOCK_ENABLE_REG_REG_OFFSET 0x4
27 #define I2SIP_RX_BLOCK_ENABLE_REG_ENABLE_SHIFT (0)
28 #define I2SIP_RX_BLOCK_ENABLE_REG_ENABLE_MASK ((0x1)<<I2SIP_RX_BLOCK_ENABLE_REG_ENABLE_SHIFT)
29 
30 /* send block enable register */
31 #define I2SIP_TX_BLOCK_ENABLE_REG_REG_OFFSET 0x8
32 #define I2SIP_TX_BLOCK_ENABLE_REG_ENABLE_SHIFT (0)
33 #define I2SIP_TX_BLOCK_ENABLE_REG_ENABLE_MASK ((0x1)<<I2SIP_TX_BLOCK_ENABLE_REG_ENABLE_SHIFT)
34 
35 /* clk gen enable register */
36 #define I2SIP_CLK_GEN_ENABLE_REG_REG_OFFSET 0xc
37 #define I2SIP_CLK_GEN_ENABLE_REG_ENABLE_SHIFT (0)
38 #define I2SIP_CLK_GEN_ENABLE_REG_ENABLE_MASK ((0x1)<<I2SIP_CLK_GEN_ENABLE_REG_ENABLE_SHIFT)
39 
40 /* clk config register */
41 #define I2SIP_CLK_CFG_REG_OFFSET 0x10
42 #define I2SIP_CLK_CFG_WSS_SHIFT (3)
43 #define I2SIP_CLK_CFG_WSS_MASK ((0x3)<<I2SIP_CLK_CFG_WSS_SHIFT)
44 #define I2SIP_CLK_CFG_WSS_VAL_16CYCLE 0
45 #define I2SIP_CLK_CFG_WSS_VAL_24CYCLE 1
46 #define I2SIP_CLK_CFG_WSS_VAL_32CYCLE 2
47 
48 #define I2SIP_CLK_CFG_SCLK_GATE_SHIFT (0)
49 #define I2SIP_CLK_CFG_SCLK_GATE_MASK ((0x7)<<I2SIP_CLK_CFG_SCLK_GATE_SHIFT)
50 #define I2SIP_CLK_CFG_SCLK_GATE_VAL_NO_GATE 0
51 #define I2SIP_CLK_CFG_SCLK_GATE_VAL_12_GATE 1
52 #define I2SIP_CLK_CFG_SCLK_GATE_VAL_16_GATE 2
53 #define I2SIP_CLK_CFG_SCLK_GATE_VAL_20_GATE 3
54 #define I2SIP_CLK_CFG_SCLK_GATE_VAL_24_GATE 4
55 
56 /* recv block fifo reset register */
57 #define I2SIP_RX_BLOCK_FIFO_RESET_REG_OFFSET 0x14
58 #define I2SIP_RX_BLOCK_FIFO_RESET_RESET_SHIFT (0)
59 #define I2SIP_RX_BLOCK_FIFO_RESET_RESET_MASK ((0x1)<<I2SIP_RX_BLOCK_FIFO_RESET_RESET_SHIFT)
60 
61 /* send block fifo reset register */
62 #define I2SIP_TX_BLOCK_FIFO_RESET_REG_OFFSET 0x18
63 #define I2SIP_TX_BLOCK_FIFO_RESET_RESET_SHIFT (0)
64 #define I2SIP_TX_BLOCK_FIFO_RESET_RESET_MASK ((0x1)<<I2SIP_TX_BLOCK_FIFO_RESET_RESET_SHIFT)
65 
66 /* left recv buffer register */
67 #define I2SIP_LEFT_RX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x20)
68 
69 /* left send buffer register */
70 #define I2SIP_LEFT_TX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x20)
71 
72 /* right recv buffer register */
73 #define I2SIP_RIGHT_RX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x24)
74 
75 /* right send buffer register */
76 #define I2SIP_RIGHT_TX_BUFF_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x24)
77 
78 /* channel 0 */
79 /* recv enable register */
80 #define I2SIP_RX_ENABLE_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x28)
81 #define I2SIP_RX_ENABLE_ENABLE_SHIFT (0)
82 #define I2SIP_RX_ENABLE_ENABLE_MASK ((0x1)<<I2SIP_RX_ENABLE_ENABLE_SHIFT)
83 
84 /* send enable register */
85 #define I2SIP_TX_ENABLE_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x2c)
86 #define I2SIP_TX_ENABLE_ENABLE_SHIFT (0)
87 #define I2SIP_TX_ENABLE_ENABLE_MASK ((0x1)<<I2SIP_TX_ENABLE_ENABLE_SHIFT)
88 
89 /* recv config register */
90 #define I2SIP_RX_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x30)
91 #define I2SIP_RX_CFG_WLEN_SHIFT (0)
92 #define I2SIP_RX_CFG_WLEN_MASK ((0x7)<<I2SIP_RX_CFG_WLEN_SHIFT)
93 #define I2SIP_RX_CFG_WLEN_VAL_IGNORE 0
94 #define I2SIP_RX_CFG_WLEN_VAL_12BIT 1
95 #define I2SIP_RX_CFG_WLEN_VAL_16BIT 2
96 #define I2SIP_RX_CFG_WLEN_VAL_20BIT 3
97 #define I2SIP_RX_CFG_WLEN_VAL_24BIT 4
98 #define I2SIP_RX_CFG_WLEN_VAL_32BIT 5
99 
100 /* send config register */
101 #define I2SIP_TX_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x34)
102 #define I2SIP_TX_CFG_WLEN_SHIFT (0)
103 #define I2SIP_TX_CFG_WLEN_MASK ((0x7)<<I2SIP_TX_CFG_WLEN_SHIFT)
104 #define I2SIP_TX_CFG_WLEN_VAL_IGNORE 0
105 #define I2SIP_TX_CFG_WLEN_VAL_12BIT 1
106 #define I2SIP_TX_CFG_WLEN_VAL_16BIT 2
107 #define I2SIP_TX_CFG_WLEN_VAL_20BIT 3
108 #define I2SIP_TX_CFG_WLEN_VAL_24BIT 4
109 #define I2SIP_TX_CFG_WLEN_VAL_32BIT 5
110 
111 /* recv or send config register */
112 #define I2SIP_CFG_WLEN_VAL_IGNORE 0
113 #define I2SIP_CFG_WLEN_VAL_12BIT  1
114 #define I2SIP_CFG_WLEN_VAL_16BIT  2
115 #define I2SIP_CFG_WLEN_VAL_20BIT  3
116 #define I2SIP_CFG_WLEN_VAL_24BIT  4
117 #define I2SIP_CFG_WLEN_VAL_32BIT  5
118 
119 
120 /* int status register */
121 #define I2SIP_INT_STATUS_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x38)
122 #define I2SIP_INT_STATUS_TX_FIFO_OVER_SHIFT (5)
123 #define I2SIP_INT_STATUS_TX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_STATUS_TX_FIFO_OVER_SHIFT)
124 #define I2SIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT (4)
125 #define I2SIP_INT_STATUS_TX_FIFO_EMPTY_MASK ((0x1)<<I2SIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT)
126 #define I2SIP_INT_STATUS_RX_FIFO_OVER_SHIFT (1)
127 #define I2SIP_INT_STATUS_RX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_STATUS_RX_FIFO_OVER_SHIFT)
128 #define I2SIP_INT_STATUS_RX_FIFO_DA_SHIFT (0)
129 #define I2SIP_INT_STATUS_RX_FIFO_DA_MASK ((0x1)<<I2SIP_INT_STATUS_RX_FIFO_DA_SHIFT)
130 
131 /* int mask register */
132 #define I2SIP_INT_MASK_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x3c)
133 #define I2SIP_INT_MASK_TX_FIFO_OVER_SHIFT (5)
134 #define I2SIP_INT_MASK_TX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_MASK_TX_FIFO_OVER_SHIFT)
135 #define I2SIP_INT_MASK_TX_FIFO_EMPTY_SHIFT (4)
136 #define I2SIP_INT_MASK_TX_FIFO_EMPTY_MASK ((0x1)<<I2SIP_INT_MASK_TX_FIFO_EMPTY_SHIFT)
137 #define I2SIP_INT_MASK_RX_FIFO_OVER_SHIFT (1)
138 #define I2SIP_INT_MASK_RX_FIFO_OVER_MASK ((0x1)<<I2SIP_INT_MASK_RX_FIFO_OVER_SHIFT)
139 #define I2SIP_INT_MASK_RX_FIFO_DA_SHIFT (0)
140 #define I2SIP_INT_MASK_RX_FIFO_DA_MASK ((0x1)<<I2SIP_INT_MASK_RX_FIFO_DA_SHIFT)
141 #define I2SIP_INT_MASK_ALL \
142     (I2SIP_INT_MASK_TX_FIFO_OVER_MASK|I2SIP_INT_MASK_TX_FIFO_EMPTY_MASK|I2SIP_INT_MASK_RX_FIFO_OVER_MASK|I2SIP_INT_MASK_RX_FIFO_DA_MASK)
143 #define I2SIP_INT_UNMASK_ALL 0
144 
145 /* clr recv over flow register */
146 #define I2SIP_CLR_RX_OVER_FLOW_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x40)
147 #define I2SIP_CLR_RX_OVER_FLOW_CLR_SHIFT (0)
148 #define I2SIP_CLR_RX_OVER_FLOW_CLR_MASK ((0x1)<<I2SIP_CLR_RX_OVER_FLOW_CLR_SHIFT)
149 
150 /* clr send over flow register */
151 #define I2SIP_CLR_TX_OVER_FLOW_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x44)
152 #define I2SIP_CLR_TX_OVER_FLOW_CLR_SHIFT (0)
153 #define I2SIP_CLR_TX_OVER_FLOW_CLR_MASK ((0x1)<<I2SIP_CLR_TX_OVER_FLOW_CLR_SHIFT)
154 
155 /* recv fifo config register */
156 #define I2SIP_RX_FIFO_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x48)
157 #define I2SIP_RX_FIFO_CFG_LEVEL_SHIFT (0)
158 #define I2SIP_RX_FIFO_CFG_LEVEL_MASK ((0xf)<<I2SIP_RX_FIFO_CFG_LEVEL_SHIFT)
159 
160 /* send fifo config register */
161 #define I2SIP_TX_FIFO_CFG_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x4c)
162 #define I2SIP_TX_FIFO_CFG_LEVEL_SHIFT (0)
163 #define I2SIP_TX_FIFO_CFG_LEVEL_MASK ((0xf)<<I2SIP_TX_FIFO_CFG_LEVEL_SHIFT)
164 
165 /* recv fifo flush register */
166 #define I2SIP_RX_FIFO_FLUSH_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x50)
167 #define I2SIP_RX_FIFO_FLUSH_SHIFT (0)
168 #define I2SIP_RX_FIFO_FLUSH_MASK ((0x1)<<I2SIP_RX_FIFO_FLUSH_SHIFT)
169 
170 /* send fifo flush register */
171 #define I2SIP_TX_FIFO_FLUSH_REG_OFFSET(c) I2SIP_CHAN_REG(c, 0x54)
172 #define I2SIP_TX_FIFO_FLUSH_SHIFT (0)
173 #define I2SIP_TX_FIFO_FLUSH_MASK ((0x1)<<I2SIP_TX_FIFO_FLUSH_SHIFT)
174 
175 /* dma ctrl register */
176 #ifdef CHIP_BEST1000
177 #define I2SIP_DMA_CTRL_REG_OFFSET 0x58
178 #define I2SIP_DMA_CTRL_RX_ENABLE_SHIFT (0)
179 #define I2SIP_DMA_CTRL_RX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_RX_ENABLE_SHIFT)
180 #define I2SIP_DMA_CTRL_TX_ENABLE_SHIFT (1)
181 #define I2SIP_DMA_CTRL_TX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_TX_ENABLE_SHIFT)
182 #else
183 #define I2SIP_DMA_CTRL_REG_OFFSET 0x1c8
184 #define I2SIP_DMA_CTRL_RX_ENABLE_SHIFT (0)
185 #define I2SIP_DMA_CTRL_RX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_RX_ENABLE_SHIFT)
186 #define I2SIP_DMA_CTRL_TX_ENABLE_SHIFT (1)
187 #define I2SIP_DMA_CTRL_TX_ENABLE_MASK ((0x1)<<I2SIP_DMA_CTRL_TX_ENABLE_SHIFT)
188 #define I2SIP_DMA_CTRL_RX_1_CHAN_SHIFT (2)
189 #define I2SIP_DMA_CTRL_RX_1_CHAN_MASK (1 << I2SIP_DMA_CTRL_RX_1_CHAN_SHIFT)
190 #define I2SIP_DMA_CTRL_TX_1_CHAN_SHIFT (3)
191 #define I2SIP_DMA_CTRL_TX_1_CHAN_MASK (1 << I2SIP_DMA_CTRL_TX_1_CHAN_SHIFT)
192 #define I2SIP_DMA_CTRL_RX_CHAN_SEL_SHIFT (4)
193 #define I2SIP_DMA_CTRL_RX_CHAN_SEL_MASK (3 << I2SIP_DMA_CTRL_RX_CHAN_SEL_SHIFT)
194 #define I2SIP_DMA_CTRL_RX_CHAN_SEL(n) BITFIELD_VAL(I2SIP_DMA_CTRL_RX_CHAN_SEL, n)
195 #define I2SIP_DMA_CTRL_TX_CHAN_SEL_SHIFT (6)
196 #define I2SIP_DMA_CTRL_TX_CHAN_SEL_MASK (3 << I2SIP_DMA_CTRL_TX_CHAN_SEL_SHIFT)
197 #define I2SIP_DMA_CTRL_TX_CHAN_SEL(n) BITFIELD_VAL(I2SIP_DMA_CTRL_TX_CHAN_SEL, n)
198 #define I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE_SHIFT (16)
199 #define I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE_MASK (0xF << I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE_SHIFT)
200 #define I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE(n) BITFIELD_VAL(I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE, n)
201 #define I2SIP_DMA_CTRL_RX_FIFO_PUSH_REALIGN_SHIFT (20)
202 #define I2SIP_DMA_CTRL_RX_FIFO_PUSH_REALIGN_MASK (1 << I2SIP_DMA_CTRL_RX_FIFO_PUSH_REALIGN_SHIFT)
203 #define I2SIP_DMA_CTRL_RX_FIFO_POP_REALIGN_SHIFT (21)
204 #define I2SIP_DMA_CTRL_RX_FIFO_POP_REALIGN_MASK (1 << I2SIP_DMA_CTRL_RX_FIFO_POP_REALIGN_SHIFT)
205 #define I2SIP_DMA_CTRL_RX_DMA_BLK_EN_SHIFT (22)
206 #define I2SIP_DMA_CTRL_RX_DMA_BLK_EN_MASK (1 << I2SIP_DMA_CTRL_RX_DMA_BLK_EN_SHIFT)
207 #define I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE_SHIFT (24)
208 #define I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE_MASK (0xF << I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE_SHIFT)
209 #define I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE(n) BITFIELD_VAL(I2SIP_DMA_CTRL_TX_DMA_BLK_SIZE, n)
210 #define I2SIP_DMA_CTRL_TX_FIFO_PUSH_REALIGN_SHIFT (28)
211 #define I2SIP_DMA_CTRL_TX_FIFO_PUSH_REALIGN_MASK (1 << I2SIP_DMA_CTRL_TX_FIFO_PUSH_REALIGN_SHIFT)
212 #define I2SIP_DMA_CTRL_TX_FIFO_POP_REALIGN_SHIFT (29)
213 #define I2SIP_DMA_CTRL_TX_FIFO_POP_REALIGN_MASK (1 << I2SIP_DMA_CTRL_TX_FIFO_POP_REALIGN_SHIFT)
214 #define I2SIP_DMA_CTRL_TX_DMA_BLK_EN_SHIFT (30)
215 #define I2SIP_DMA_CTRL_TX_DMA_BLK_EN_MASK (1 << I2SIP_DMA_CTRL_TX_DMA_BLK_EN_SHIFT)
216 #endif
217 /* tdm ctrl register */
218 #define I2SIP_TDM_CTRL_REG_OFFSET 0x1d0
219 /* channel 0 end */
220 /* i2sip register end */
221 
222 #endif /* __REG_I2SIP_H_ */
223