1 /** 2 ****************************************************************************** 3 * @file hal_platform.h 4 * @author 5 * @version V1.0.0 6 * @date 2016-05-17 7 * @brief This file contains all the definations of platform. 8 ****************************************************************************** 9 * @attention 10 * 11 * This module is a confidential and proprietary property of RealTek and 12 * possession or use of this module requires written permission of RealTek. 13 * 14 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved. 15 ****************************************************************************** 16 */ 17 #ifndef _HAL_PLATFORM_ 18 #define _HAL_PLATFORM_ 19 20 #define ROMVERSION 0x01 /* ACUT is 0x01, BCUT is 0x02 ... */ 21 #define ROMVERSION_SUB 2 /* ROM sub version */ 22 #define ROMINFORMATION (ROMVERSION) 23 24 #define HAL_READ32(base, addr) rtk_le32_to_cpu(*((volatile u32*)(base + addr))) 25 #define HAL_WRITE32(base, addr, value32) ((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32)) 26 #define HAL_READ16(base, addr) rtk_le16_to_cpu(*((volatile u16*)(base + addr))) 27 #define HAL_WRITE16(base, addr, value) ((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value)) 28 #define HAL_READ8(base, addr) (*((volatile u8*)(base + addr))) 29 #define HAL_WRITE8(base, addr, value) ((*((volatile u8*)(base + addr))) = value) 30 31 32 #ifdef __cplusplus 33 #define __I volatile /*!< Defines 'read only' permissions */ 34 #else 35 #define __I volatile const /*!< Defines 'read only' permissions */ 36 #endif 37 #define __O volatile /*!< Defines 'write only' permissions */ 38 #define __IO volatile /*!< Defines 'read / write' permissions */ 39 40 /**************************************************************************//** 41 * @defgroup AmebaD_Outline 42 * @{ 43 *****************************************************************************/ 44 45 /** @addtogroup AmebaD_Outline 46 * @verbatim 47 ***************************************************************************************** 48 * CPU 49 ***************************************************************************************** 50 * -Clock speed: 125MHz 51 * -Core: CM4F 52 * -Working votage: 3.3V 53 * 54 ***************************************************************************************** 55 * Memory 56 ***************************************************************************************** 57 * -ROM: 512KB 58 * -RAM: 256KB 59 * -FLash: 128MB 60 * 61 ***************************************************************************************** 62 * GPIO 63 ***************************************************************************************** 64 * -GPIOA: 0~31, IN/OUT/INT 65 * -GPIOB: 0~31, IN/OUT/INT 66 * 67 ***************************************************************************************** 68 * Flash 69 ***************************************************************************************** 70 * -Max. speed: 100MHz 71 * -SPI Mode: Quad IO mode 72 * -cache: 32K I/D read cache 73 * -XIP: support executed in place 74 * 75 ***************************************************************************************** 76 * Firmware Protection 77 ***************************************************************************************** 78 * -RSIP(OTF):(Realsil Image Protection) 79 * -Flash Encryption 80 * -key store in OTP EFUSE Area, and can not read 81 * -RDP 82 * -4K RAM read protection 83 * -key store in OTP EFUSE Area, and can not read 84 * 85 ***************************************************************************************** 86 * UART 87 ***************************************************************************************** 88 * -Set count: 2 89 * -IrDA: support 90 * -Low Power: support 91 * -Sleep wakeup: support 92 * -Baud rate: 110~6000000 93 * -GDMA: support 94 * 95 ***************************************************************************************** 96 * UART LOG 97 ***************************************************************************************** 98 * -Set count: 1 99 * -IrDA: support 100 * -Low Power: not support 101 * -Sleep wakeup: not support 102 * -Baud rate: 110~6000000 103 * 104 ***************************************************************************************** 105 * SPI Master 106 ***************************************************************************************** 107 * -Set count: 1 108 * -Max. Speed: 31.25MHz 109 * -GDMA: support 110 * 111 ***************************************************************************************** 112 * SPI Slave 113 ***************************************************************************************** 114 * -Set count: 1 115 * -Max. Speed: 31.25MHz 116 * -GDMA: support 117 * 118 ***************************************************************************************** 119 * I2C 120 ***************************************************************************************** 121 * -Set count: 1 122 * -Speed: Standard (up to 100 kHz) and Fast (up to 400 kHz) Modes 123 * -Role: Master & Slave 124 * -Sleep wakeup: support 125 * -GDMA: support 126 * 127 ***************************************************************************************** 128 * RTC 129 ***************************************************************************************** 130 * -Set count: 1 131 * -H: 12/24 hour mode 132 * -M: 0~59 133 * -S: 0~59 134 * -D: 0~511 135 * -Alarm: support D/H/M/S 136 * -Daylight: support 137 * -Calibration: support 138 * 139 ***************************************************************************************** 140 * PWM 141 ***************************************************************************************** 142 * -Channel count: 6(KM0)/18(KM4) 143 * -Max. Resolution: 16bits (customizable) 144 * -Max. Frequency: 40MHz@1-bit mode, 40/(2^x))MHz@x-bit 145 * 146 ***************************************************************************************** 147 * Capture 148 ***************************************************************************************** 149 * -Channel count: 1 150 * -Max. Resolution: 16bits (customizable) 151 * -Max. Frequency: 40MHz@1-bit mode, 40/(2^x))MHz@x-bit 152 * -capture width: supoort 153 * -capture number: support 154 * 155 ***************************************************************************************** 156 * Timer 157 ***************************************************************************************** 158 * -Set count: 12 159 * -32KHz timer: 8 160 * -40MHz timer: 4 161 * 162 ***************************************************************************************** 163 * I2S 164 ***************************************************************************************** 165 * -Set count: 1 166 * -Source clk: 45.1584MHz or 98.304MHz(default) 167 * -Sample rate: 8K, 12K, 16K, 24K, 32K, 48K, 64K, 96K, 192K, 384K, 7.35K, 11.025K, 14.7K, 22.05K, 29.4K, 44.1K, 58.8K, 88.2K, 176.4K 168 * -Sample bit: 16 bit, 24 bit 169 * -DMA: support 170 * 171 ***************************************************************************************** 172 * WIFI 173 ***************************************************************************************** 174 * -Set count: 1 175 * -Mode: B/G/N(2.4G) 176 * -BW: 20MHz/40MHz 177 * -Ant: 1T/1R 178 * 179 ***************************************************************************************** 180 * USB device 181 ***************************************************************************************** 182 * -Set count: 1 183 * -DMA: support 184 * 185 ***************************************************************************************** 186 * SDIO device 187 ***************************************************************************************** 188 * -Set count: 1 189 * -GSPI: support 190 * -DMA: support 191 * 192 ***************************************************************************************** 193 * BACKUP REG 194 ***************************************************************************************** 195 * -Set count: 4 dwords 196 * 197 ***************************************************************************************** 198 * CRYPTO 199 ***************************************************************************************** 200 * -MD5 201 * -SHA1 202 * -SHA2 203 * -HMAC-MD5 204 * -HMAC-SHA1 205 * -HMAC-SHA2 206 * 207 * -AES-CBC 208 * -AES-ECB 209 * -AES-CTR 210 * -AES-CFB 211 * -AES-OFB 212 * -AES-GCM 213 * -3DES-CBC 214 * -3DES-ECB 215 * -DES-CBC 216 * -DES-ECB 217 * 218 ***************************************************************************************** 219 * ADC 220 ***************************************************************************************** 221 * -Set count: 1 222 * -Channel: 4 223 * -Sample rate: max frequency up to 1MHz per channel, configurable 224 * -Resolution: 12 bit 225 * -signal sampling: CH1 & CH3: 0 ~ 3V, CH2: 0~5V 226 * -power save: Support one shot mode 227 * -GDMA: support 228 * 229 ***************************************************************************************** 230 * GDMA 231 ***************************************************************************************** 232 * -Set count: 2 233 * -Channel: 2*6 234 * 235 ***************************************************************************************** 236 * @endverbatim 237 */ 238 239 /**************************************************************************//** 240 * @defgroup AmebaD_Address_Map AmebaD HS/LP Address Map 241 * @{ 242 *****************************************************************************/ 243 #if defined (ARM_CORE_CM4) 244 #define SYSTEM_CTRL_BASE 0x40000000 245 #define PERI_ON_BASE 0x40000000 246 #define VENDOR_REG_BASE 0x40002800 247 #else 248 #define SYSTEM_CTRL_BASE 0x48000000 249 #define PERI_ON_BASE 0x48000000 250 #define VENDOR_REG_BASE 0x48002800 251 #endif 252 #define LP_RW_HSYSON_OFFSET 0x00000800 //use LP_RW_HSYSON_OFFSET can access HS SYSON directly when KM4 power gate 253 #define SYSTEM_CTRL_BASE_HP 0x40000000 254 #define SYSTEM_CTRL_BASE_HP_S 0x50000000 255 #define SYSTEM_CTRL_BASE_LP 0x48000000 256 #define PINMUX_REG_BASE 0x48000400 /* 0x0400~0x05FF */ 257 #define RSIP_REG_BASE 0x48000600 /* 0x0600~0x07FF */ 258 259 #define TIMERM4_REG_BASE 0x40002000 260 #define TIMERM0_REG_BASE 0x48002000 /*KM0 LTimer */ 261 262 #define UART0_REG_BASE 0x40004000 /*KM4 uart0 */ 263 #define UART1_REG_BASE 0x4000A000 /*KM4 uart1_bt */ 264 #define UART2_REG_BASE 0x48012000 /*KM0 log uart */ 265 #define UART3_REG_BASE 0x4800E000 /*KM0 luart */ 266 #define UARTLOG_REG_BASE UART2_REG_BASE /*KM0 log uart */ 267 268 #define IPCM4_REG_BASE 0x40006000 269 #define IPCM0_REG_BASE 0x48006000 /*KM0 IPC */ 270 271 #define USI_REG_BASE 0x40008000 272 #define RXI300M4_REG_BASE 0x4000C000 273 #define RXI300M0_REG_BASE 0x48018000 /*KM0 RXI300 */ 274 #define SPI1_REG_BASE 0x4000E000 275 #define SPI0_REG_BASE 0x40078000 276 277 #define AUDIO_SI_REG_BASE 0x40010000 278 #define AUDIO_SPORT_REG_BASE 0x40010800 279 #define IR_REG_BASE 0x40012000 280 #define PSRAM_REG_BASE 0x40014000 281 #define PSRAM_BASE 0x02000000 282 283 #define I2S0_REG_BASE 0x40020000 284 #define CRYPTO_REG_BASE 0x40022000 285 #define CRYPTOS_REG_BASE 0x50022000 286 #define SDIOH_REG_BASE 0x40026000 287 #if defined (ARM_CORE_CM4) 288 #define GDMA0_REG_BASE 0x4002A000 /*KM4 GDMA */ 289 #else 290 #define GDMA0_REG_BASE 0x48010000 /*KM0 GDMA */ 291 #endif 292 #define GDMA0S_REG_BASE 0x5002A000 /*KM4 GDMAS */ 293 294 #define SDIO_DEVICE_REG_BASE 0x4002C000 295 #define USB_OTG_REG_BASE 0x40040000 296 #define LCDC_REG_BASE 0x40070000 297 298 #define WIFI_REG_BASE 0x40080000 299 #define WIFI_BB_REG_BASE 0x40082800 300 #define WIFI_RF_REG_BASE 0x40083800 301 302 #define SPI_FLASH_CTRL_BASE 0x48080000 303 #define SPI_FLASH_BASE 0x08000000 304 305 #define RTC_BASE 0x48004000 /*KM0 RTC */ 306 #define CTC_REG_BASE 0x4801c000 /*KM0 Cap-Touch */ 307 #define KEYSCAN_REG_BASE 0x4800A000 /*KM0 Key-Scan */ 308 #define I2C0_REG_BASE 0x4800C000 /*KM0 I2C0 */ 309 310 #define GPIO_REG_BASE 0x48014000 /*KM0 GPIO */ 311 #define SGPIO_REG_BASE 0x4801A000 /*KM0 SGPIO */ 312 #define ADC_REG_BASE 0x4801C800 /*KM0 ADC */ 313 #define CMP_REG_BASE 0x4801CC00 /*KM0 COMPARE*/ 314 #define QDEC_REG_BASE 0x4801E000 /*KM0 QDEC */ 315 316 #define KM4_IDAU_BASE 0x5000C100 317 318 #define BACKUP_REG_BASE 0x480003C0 /*KM0 BACKUP REG */ 319 #define WDG_REG_BASE VENDOR_REG_BASE 320 321 /* 1024B Retention Ram base address */ 322 #define RETENTION_RAM_BASE 0x000C0000 323 #define RETENTION_RAM_SYS_OFFSET 0x80 324 #define RETENTION_RAM_WIFI_FW_OFFSET 0x130 /* 0x000C_0130~0x000C_0400-1: 720B for wifi firmware */ 325 #define RETENTION_RAM_WIFI_FW_SIZE 720 326 327 #ifdef DEBUG 328 #undef DEBUG 329 #define __todo__debug__ 330 #endif 331 332 /** @} End of group AmebaD_Address_Map */ 333 334 /**************************************************************************//** 335 * @defgroup AmebaD_Peripheral_Registers_Structures AmebaD Peripheral_Registers_Structures 336 * @{ 337 *****************************************************************************/ 338 339 /**************************************************************************//** 340 * @defgroup AMEBAD_IDAU 341 * @{ 342 * @brief AMEBAD_IDAU Register Declaration 343 *****************************************************************************/ 344 typedef struct { 345 __IO u32 IDAU_BARx; /*!< , Address offset: 0x00 */ 346 __IO u32 IDAU_LARx; /*!< , Address offset: 0x04 */ 347 } IDAU_EntryTypeDef; 348 349 typedef struct { 350 IDAU_EntryTypeDef ENTRY[8]; /*!< , Address offset: 0x00 ~ 0x3C*/ 351 __IO u32 IDAU_CTRL; /*!< , Address offset: 0x40 */ 352 __IO u32 IDAU_LOCK; /*!< , Address offset: 0x44 */ 353 } IDAU_TypeDef; 354 /** @} */ 355 356 /**************************************************************************//** 357 * @defgroup AMEBAD_WDG 358 * @{ 359 * @brief AMEBAD_WDG Register Declaration 360 *****************************************************************************/ 361 typedef struct { 362 __IO u32 VENDOR; /*!< WDG VENDOR register, Address offset: 0x00 */ 363 } WDG_TypeDef; 364 /** @} */ 365 366 /**************************************************************************//** 367 * @defgroup AMEBAD_UART 368 * @{ 369 * @brief AMEBAD_UART Register Declaration 370 *****************************************************************************/ 371 typedef struct { 372 __IO u32 DLL; /*!< UART Divisor Latch register(not used in Amebaz), Address offset: 0x00*/ 373 __IO u32 DLH_INTCR; /*!< UART interrupt enable register, Address offset: 0x04*/ 374 __IO u32 INTID; /*!< UART interrupt identification register, Address offset: 0x08*/ 375 __IO u32 LCR; /*!< UART line control register, Address offset: 0x0C*/ 376 __IO u32 MCR; /*!< UART modem control register, Address offset: 0x10*/ 377 __I u32 LSR; /*!< UART line status register, Address offset: 0x14*/ 378 __I u32 MDSR; /*!< UART modem status register, Address offset: 0x18*/ 379 __IO u32 SPR; /*!< UART scratch pad register, Address offset: 0x1C*/ 380 __IO u32 STSR; /*!< UART STS register, Address offset: 0x20*/ 381 __IO u32 RB_THR; /*!< UART receive buffer/transmitter holding register, Address offset: 0x24*/ 382 __IO u32 MISCR; /*!< UART MISC control register, Address offset: 0x28*/ 383 __IO u32 TXPLSR; /*!< UART IrDA SIR TX Pulse Width Control register, Address offset: 0x2C*/ 384 385 __IO u32 RXPLSR; /*!< UART IrDA SIR RX Pulse Width Control register, Address offset: 0x30*/ 386 __IO u32 BAUDMONR; /*!< UART baud monitor register, Address offset: 0x34*/ 387 __IO u32 RSVD2; /*!< UART reserved field, Address offset: 0x38*/ 388 __IO u32 DBG_UART; /*!< UART debug register, Address offset: 0x3C*/ 389 390 /* AmebaZ add for power save */ 391 __IO u32 RX_PATH; /*!< UART rx path control register, Address offset: 0x40*/ 392 __IO u32 MON_BAUD_CTRL; /*!< UART monitor baud rate control register, Address offset: 0x44*/ 393 __IO u32 MON_BAUD_STS; /*!< UART monitor baud rate status register, Address offset: 0x48*/ 394 __IO u32 MON_CYC_NUM; /*!< UART monitor cycle number register, Address offset: 0x4c*/ 395 __IO u32 RX_BYTE_CNT; /*!< UART rx byte counter register, Address offset: 0x50*/ 396 397 /* AmebaZ change */ 398 __IO u32 FCR; /*!< UART FIFO Control register, Address offset: 0x54*/ 399 } UART_TypeDef; 400 /** @} */ 401 402 /**************************************************************************//** 403 * @defgroup AMEBAD_SPI 404 * @{ 405 * @brief AMEBAD_SPI Register Declaration 406 *****************************************************************************/ 407 typedef struct { 408 __IO uint32_t CTRLR0; /*!< SSI control register 0, Address offset: 0x00 */ 409 __IO uint32_t CTRLR1; /*!< SSI control register 1, Address offset: 0x04 */ 410 __IO uint32_t SSIENR; /*!< SSI enable register, Address offset: 0x08 */ 411 __IO uint32_t MWCR; /*!< SSI microwire control register, Address offset: 0x0C */ 412 __IO uint32_t SER; /*!< SSI slave enable register, Address offset: 0x10 */ 413 __IO uint32_t BAUDR; /*!< SSI baud rate select register, Address offset: 0x14 */ 414 __IO uint32_t TXFTLR; /*!< SSI transmit FIFO threshold level register, Address offset: 0x18 */ 415 __IO uint32_t RXFTLR; /*!< SSI receive FIFO Threshold Level register, Address offset: 0x1C */ 416 __I uint32_t TXFLR; /*!< SSI transmit FIFO level register, Address offset: 0x20 */ 417 __I uint32_t RXFLR; /*!< SSI receive FIFO level register, Address offset: 0x24*/ 418 __I uint32_t SR; /*!< SSI status register, Address offset: 0x28 */ 419 __IO uint32_t IMR; /*!< SSI interrupt mask register, Address offset: 0x2C */ 420 __I uint32_t ISR; /*!< SSI interrupt status register, Address offset: 0x30 */ 421 __I uint32_t RISR; /*!< SSI raw interrupt status register, Address offset: 0x34 */ 422 __I uint32_t TXOICR; /*!< SSI transmit FIFO overflow interrupt clear register, Address offset: 0x38 */ 423 __I uint32_t RXOICR; /*!< SSI receive FIFO overflow interrupt clear register, Address offset: 0x3C */ 424 __I uint32_t RXUICR; /*!< SSI receive FIFO underflow interrupt clear register, Address offset: 0x40 */ 425 __I uint32_t MSTICR; /*!< SSI multi-master interrupt clear register, Address offset: 0x44 */ 426 __I uint32_t ICR; /*!< SSI interrupt clear register, Address offset: 0x48 */ 427 __IO uint32_t DMACR; /*!< SSI DMA control register, Address offset: 0x4C */ 428 __IO uint32_t DMATDLR; /*!< SSI DMA transmit data level register, Address offset: 0x50 */ 429 __IO uint32_t DMARDLR; /*!< SSI DMA receive data level register, Address offset: 0x54 */ 430 __I uint32_t IDR; /*!< SSI identification register, Address offset: 0x58 */ 431 __I uint32_t SSI_COMP_VERSION; /*!< SSI coreKit version ID register, Address offset: 0x5C */ 432 __IO uint32_t DR[36]; /*!< SSI data register, Address offset: 0x60 - 0xEC */ 433 __IO uint32_t RX_SAMPLE_DLY; /*!< SSI rxd sample delay register, Address offset: 0xF0 */ 434 }SPI_TypeDef; 435 /** @} */ 436 437 /**************************************************************************//** 438 * @defgroup AMEBAD_SPIC 439 * @{ 440 * @brief AMEBAD_SPIC Register Declaration 441 *****************************************************************************/ 442 typedef struct 443 { 444 __IO uint32_t ctrlr0; /*!< SPIC control register0, Address offset: 0x000 */ 445 __IO uint32_t ctrlr1; /*!< SPIC control register1, Address offset: 0x004 */ 446 __IO uint32_t ssienr; /*!< SPIC enable register, Address offset: 0x008 */ 447 __IO uint32_t mwcr; /*!< N/A, Address offset: 0x00C */ 448 __IO uint32_t ser; /*!< SPIC slave enable register, Address offset: 0x010 */ 449 __IO uint32_t baudr; /*!< SPIC baudrate select register, Address offset: 0x014 */ 450 __IO uint32_t txftlr; /*!< SPIC transmit FIFO threshold level, Address offset: 0x018 */ 451 __IO uint32_t rxftlr; /*!< SPIC receive FIFO threshold level, Address offset: 0x01C */ 452 __IO uint32_t txflr; /*!< SPIC transmit FIFO level register, Address offset: 0x020 */ 453 __IO uint32_t rxflr; /*!< SPIC receive FIFO level register, Address offset: 0x024 */ 454 __IO uint32_t sr; /*!< SPIC status register, Address offset: 0x028 */ 455 __IO uint32_t imr; /*!< SPIC interrupt mask register, Address offset: 0x02C */ 456 __IO uint32_t isr; /*!< SPIC interrupt status register, Address offset: 0x030 */ 457 __IO uint32_t risr; /*!< SPIC raw interrupt status register, Address offset: 0x034 */ 458 __IO uint32_t txoicr; /*!< SPIC transmit FIFO overflow interrupt clear register, Address offset: 0x038 */ 459 __IO uint32_t rxoicr; /*!< SPIC receive FIFO overflow interrupt clear register, Address offset: 0x03C */ 460 __IO uint32_t rxuicr; /*!< SPIC receive FIFO underflow interrupt clear register, Address offset: 0x040 */ 461 __IO uint32_t msticr; /*!< SPIC master error interrupt clear register, Address offset: 0x044 */ 462 __IO uint32_t icr; /*!< SPIC interrupt clear register, Address offset: 0x048 */ 463 __IO uint32_t dmacr; /*!< N/A, Address offset: 0x04C */ 464 __IO uint32_t dmatdlr; /*!< N/A, Address offset: 0x050 */ 465 __IO uint32_t dmardlr; /*!< N/A, Address offset: 0x054 */ 466 __IO uint32_t idr; /*!< SPIC Identiation register, Address offset: 0x058 */ 467 __IO uint32_t spi_flash_version; /*!< SPIC version ID register, Address offset: 0x05C */ 468 union{ 469 __IO uint8_t byte; 470 __IO uint16_t half; 471 __IO uint32_t word; 472 } dr[32]; /*!< SPIC data register, Address offset: 0x060~0x0DC */ 473 __IO uint32_t rd_fast_single; /*!< Fast read data command of SPI Flash, Address offset: 0x0E0 */ 474 __IO uint32_t rd_dual_o; /*!< Dual output read command of SPI Flash, Address offset: 0x0E4 */ 475 __IO uint32_t rd_dual_io; /*!< Dual I/O read command of SPI Flash, Address offset: 0x0E8 */ 476 __IO uint32_t rd_quad_o; /*!< Quad output read command of SPI Flash, Address offset: 0x0EC */ 477 __IO uint32_t rd_quad_io; /*!< Quad I/O read command of SPI Flash, Address offset: 0x0F0 */ 478 __IO uint32_t wr_single; /*!< Page program command of SPI Flash, Address offset: 0x0F4 */ 479 __IO uint32_t wr_dual_i; /*!< Dual data input program command of SPI Flash, Address offset: 0x0F8 */ 480 __IO uint32_t wr_dual_ii; /*!< Dual address and data input program command of SPI Flash, Address offset: 0x0FC */ 481 __IO uint32_t wr_quad_i; /*!< Quad data input program command of SPI Flash, Address offset: 0x100 */ 482 __IO uint32_t wr_quad_ii; /*!< Quad address and data input program command of SPI Flash, Address offset: 0x104 */ 483 __IO uint32_t wr_enable; /*!< Write enabe command of SPI Flash, Address offset: 0x108 */ 484 __IO uint32_t rd_status; /*!< Read status command of SPI Flash, Address offset: 0x10C */ 485 __IO uint32_t ctrlr2; /*!< SPIC control register2, Address offset: 0x110 */ 486 __IO uint32_t fbaudr; /*!< SPIC fast baudrate select, Address offset: 0x114 */ 487 __IO uint32_t addr_length; /*!< SPIC address length register, Address offset: 0x118 */ 488 __IO uint32_t auto_length; /*!< SPIC auto address length register, Address offset: 0x11C */ 489 __IO uint32_t valid_cmd; /*!< SPIC valid command register, Address offset: 0x120 */ 490 __IO uint32_t flash_size; /*!< SPIC flash size register, Address offset: 0x124 */ 491 __IO uint32_t flush_fifo; /*!< SPIC flush FIFO register, Address offset: 0x128 */ 492 } SPIC_TypeDef; 493 /** @} */ 494 495 /**************************************************************************//** 496 * @defgroup AMEBAD_USI 497 * @{ 498 * @brief AMEBAD_USI Register Declaration 499 *****************************************************************************/ 500 501 typedef struct { 502 /*GLOBAL*/ 503 __IO u32 USI_MODE_CTRL; /*!< USI mode control register, Address offset: 0x00*/ 504 __IO u32 SW_RESET; /*!< USI software reset register, Address offset: 0x04*/ 505 506 __IO u32 RSVD0[2]; /*!< reserved space, 2 Dwords*/ 507 /*DMA*/ 508 __IO u32 DMA_ENABLE; /*!< USI DMA enable register, Address offset: 0x10*/ 509 __IO u32 DMA_REQ_SIZE; /*!< USI DMA request size register, Address offset: 0x14*/ 510 511 __IO u32 RSVD1[2]; /*!< reserved space, 2 Dwords*/ 512 513 /*TX FIFO*/ 514 __IO u32 TX_FIFO_WRITE; /*!< USI write TX FIFO register, Address offset: 0X20*/ 515 __IO u32 TX_FIFO_CTRL; /*!< USI TX FIFO control register, Address offset: 0X24*/ 516 __I u32 TX_FIFO_STATUS; /*!< USI TX FIFO status register, Address offset: 0X28*/ 517 518 __IO u32 RSVD2[1]; /*!< reserved space, 1 Dwords*/ 519 520 /*RX FIFO*/ 521 __IO u32 RX_FIFO_READ; /*!< USI RX FIFO read register, Address offset: 0X30*/ 522 __IO u32 RX_FIFO_CTRL; /*!< USI RX FIFO control register, Address offset: 0X34*/ 523 __I u32 RX_FIFO_STATUS; /*!< USI RX FIFO status register, Address offset: 0X38*/ 524 __IO u32 RX_FIFO_RD_CNT; /*!< USI RX FIFO read cnt register, Address offset: 0X3C*/ 525 526 /*INTERRUPT*/ 527 __IO u32 INTERRUPT_ENABLE; /*!< USI interrupt enable register, Address offset: 0X40*/ 528 __I u32 INTERRUPT_STATUS; /*!< USI interrupt status register, Address offset: 0X44*/ 529 __I u32 RAW_INTERRUPT_STATUS; /*!< USI interrupt raw status register, Address offset: 0X48*/ 530 __I u32 I2C_TX_ABRT_SOURCE; /*!< USI I2C abort source register, Address offset: 0X4C*/ 531 __IO u32 INTERRUPT_ALL_CLR; /*!< USI clear all interrupt register, Address offset: 0X50*/ 532 __IO u32 INTERRUPT_STATUS_CLR; /*!< USI clear interrupt register, Address offset: 0X54*/ 533 534 __IO u32 RSVD3[2]; /*!< reserved space, 2 Dwords*/ 535 536 /*DEBUG*/ 537 __IO u32 DEBUG_SEL; /*!< USI debug select register, Address offset: 0X60*/ 538 __I u32 DEBUG_PORT; /*!< USI debug port register, Address offset: 0X64*/ 539 __IO u32 ECO_USE0; /*!< USI ECO register, Address offset: 0X68*/ 540 __IO u32 ECO_USE1; /*!< USI ECO register, Address offset: 0X6C*/ 541 __IO u32 USI_COMP_VERSION; /*!< USI version number register, Address offset: 0X70*/ 542 543 __IO u32 RSVD4[35]; /*!< reserved space, 35 Dwords*/ 544 545 /*UART*/ 546 __IO u32 UART_CTRL; /*!< USI UART control register, Address offset: 0X100*/ 547 __IO u32 UART_IRDA_CTRL; /*!< USI UART IRDA control register, Address offset: 0X104*/ 548 __IO u32 UART_IRDA_TX_PULSE_WD; /*!< USI UART IRDA TX pulse configure register, Address offset: 0X108*/ 549 __IO u32 UART_IRDA_RX_PULSE_WD; /*!< USI UART IRDA RX pulse configure register, Address offset: 0X10C*/ 550 __IO u32 UART_TX_FRACTION_BAUD; /*!< USI UART TX path fraction baud rate configure register, Address offset: 0X110*/ 551 __IO u32 UART_RX_BAUD_OSC; /*!< USI UART RX baudrate configure for OSC clock, Address offset: 0X114*/ 552 __IO u32 UART_RX_BAUD_XTAL; /*!< USI UART RX baudrate configure for XTAL clock, Address offset: 0X118*/ 553 __IO u32 UART_RX_FRACTION_BAUD_CTRL; /*!< USI UART RX fraction baud rate configure register, Address offset: 0X11C*/ 554 __IO u32 UART_BAUD_MON_CTRL; /*!< USI UART baud rate monitor control register, Address offset: 0X120*/ 555 __IO u32 UART_BAUD_MON_STATUS0; /*!< USI UART baud rate monitor status register0, Address offset: 0X124*/ 556 __IO u32 UART_BAUD_MON_STATUS1; /*!< USI UART baud rate monitor status register1, Address offset: 0X128*/ 557 __IO u32 UART_TOGGLE_MON; /*!< USI UART toggle monitor register, Address offset: 0X12C*/ 558 __IO u32 UART_FLOW_CTRL; /*!< USI UART flow control register, Address offset: 0X130*/ 559 __IO u32 UART_RXFIFO_TO_TH; /*!< USI UART RX FIFO timeout threshold, Address offset: 0X134*/ 560 __IO u32 UART_RXDMA_FLOW_CTRL; /*!< USI UART RX DMA flow control, Address offset: 0X138*/ 561 562 __IO u32 RSVD5[49]; /*!< reserved space, 49 Dwords*/ 563 564 /*SPI*/ 565 __IO u32 SPI_CTRL; /*!< USI SPI control register, Address offset: 0X200*/ 566 __IO u32 SPI_TRANS_EN; /*!< USI SPI transmission enable register, Address offset: 0X204*/ 567 __I u32 SPI_TRANS_STATUS; /*!< USI SPI transmission status register, Address offset: 0X208*/ 568 569 __IO u32 RSVD6[61]; /*!< reserved space, 61 Dwords*/ 570 571 /*I2C*/ 572 __IO u32 I2C_CTRL; /*!< USI I2C control register, Address offset: 0X300*/ 573 __IO u32 I2C_SS_SCL_CNT; /*!< USI I2C standard speed clock SCL low/high count register, Address offset: 0x304 */ 574 __IO u32 I2C_FS_SCL_CNT; /*!< USI I2C fast speed clock SCL low/high count register, Address offset: 0x308 */ 575 __IO u32 I2C_HS_SCL_CNT; /*!< USI I2C high speed clock SCL low/high count register, Address offset: 0x30C */ 576 __IO u32 I2C_SDA_TIMING; /*!< USI I2C SDA timing configure register, Address offset: 0x310*/ 577 __IO u32 I2C_DIG_FILTER; /*!< USI I2C filter register, Address offset: 0x314*/ 578 __IO u32 I2C_SLV_ACK_CTRL; /*!< USI I2C slave ACK control register, Address offset: 0x318*/ 579 __IO u32 I2C_ENABLE; /*!< USI I2C enable register, Address offset: 0x31C*/ 580 __IO u32 I2C_TAR; /*!< USI I2C target address register, Address offset: 0x320*/ 581 __IO u32 I2C_DMA_CMD; /*!< USI I2C DMA command register, Address offset: 0x324*/ 582 __I u32 I2C_STATUS; /*!< USI I2C status register, Address offset: 0x328*/ 583 __IO u32 RSVD7[1]; /*!< reserved space, 1 Dwords*/ 584 __IO u32 I2C_ANA_FILTER1; /*!< USI I2C filter register 1, Address offset: 0x330*/ 585 __IO u32 I2C_ANA_FILTER2; /*!< USI I2C filter register 2, Address offset: 0x334*/ 586 __IO u32 I2C_ANA_FILTER3; /*!< USI I2C filter register 3, Address offset: 0x338*/ 587 __IO u32 I2C_ANA_FILTER4; /*!< USI I2C filter register 4, Address offset: 0x33C*/ 588 __IO u32 I2C_ANA_FILTER5; /*!< USI I2C filter register 5, Address offset: 0x340*/ 589 __IO u32 I2C_ANA_FILTER6; /*!< USI I2C filter register 6, Address offset: 0x344*/ 590 __IO u32 I2C_ANA_FILTER7; /*!< USI I2C filter register 7, Address offset: 0x348*/ 591 __IO u32 I2C_ANA_FILTER8; /*!< USI I2C filter register 8, Address offset: 0x34C*/ 592 } USI_TypeDef; 593 /** @} */ 594 595 /**************************************************************************//** 596 * @defgroup AMEBAD_LCDC 597 * @{ 598 * @brief AMEBAD_LCDC Register Declaration 599 *****************************************************************************/ 600 typedef struct { 601 /*global control*/ 602 __IO u32 LCDC_CTRL; /*!< LCDC control register, Address offset: 0x00*/ 603 __IO u32 LCDC_PLANE_SIZE; /*!< LCDC plane size configure register, Address offset: 0x04*/ 604 __IO u32 LCDC_UNDFLW_CFG; /*!< LCDC DMA FIFO underflow configure register Address offset: 0x08*/ 605 __IO u32 LCDC_DMA_MODE_CFG; /*!< LCDC DMA mode configure register Address offset: 0x0C*/ 606 __IO u32 LCDC_CLK_DIV; /*!< LCDC DCLK clock divider Address offset: 0x10*/ 607 608 __IO u32 RSVD0[3]; /*!< reserved space, 2 Dwords*/ 609 610 /*Interrupt and status*/ 611 __IO u32 LCDC_IRQ_EN; /*!< LCDC interrupt enable register Address offset: 0x20*/ 612 __IO u32 LCDC_IRQ_STATUS; /*!< LCDC interrupt status after mask and interrupt clear register Address offset: 0x24*/ 613 __I u32 LCDC_IRQ_RAW; /*!< LCDC RAW interrupt status Address offset: 0x28*/ 614 __IO u32 LCDC_LINE_INT_POS; /*!< LCDC line interrupt position Address offset: 0x2C*/ 615 __I u32 LCDC_CUR_POS_STATUS; /*!< LCDC current position status register Address offset: 0x30*/ 616 __I u32 LCDC_STATUS; /*!< LCDC DMA FIFO underflow interrupt count register Address offset: 0x34*/ 617 618 __IO u32 RSVD1[2]; /*!< reserved space, 2 Dwords*/ 619 620 /*RGB control*/ 621 __IO u32 LCDC_RGB_CFG; /*!< LCDC RGB configuration register Address offset: 0x40*/ 622 __IO u32 LCDC_RGB_VSYNC_CFG; /*!< LCDC RGB vertical synchronization configuration register Address offset: 0x44*/ 623 __IO u32 LCDC_RGB_HSYNC_CFG; /*!< LCDC RGB horizontal synchronization configuration register Address offset: 0x48*/ 624 __IO u32 LCDC_RGB_SYNC_STATUS; /*!< LCDC RGB synchronization status register Address offset: 0x4C*/ 625 626 __IO u32 RSVD2[4]; /*!< reserved space, 4 Dwords*/ 627 628 /*MCU control*/ 629 __IO u32 LCDC_MCU_CFG; /*!< LCDC MCU I/F configuration register Address offset: 0x60*/ 630 __IO u32 LCDC_MCU_VSYNC_CFG; /*!< LCDC MCU I/F vertical synchronization configuration register Address offset: 0x64*/ 631 __IO u32 LCDC_MCU_TIMING_CFG; /*!< LCDC MCU I/F timing configuration register Address offset: 0x68*/ 632 __IO u32 LCDC_MCU_IO_DATA; /*!< LCDC MCU I/F write/read data register Address offset: 0x6C*/ 633 __IO u32 LCDC_MCU_IO_TO_CFG; /*!< LCDC MCU I/F IO write/read timeout configuration register Address offset: 0x70*/ 634 635 __IO u32 RSVD3[3]; /*!< reserved space, 3 Dwords*/ 636 637 /*LED control*/ 638 __IO u32 LCDC_LED_CFG; /*!< LCDC LED I/F configuration register Address offset: 0x80*/ 639 __IO u32 LCDC_LED_TIMING; /*!< LCDC LED I/F timing configuration register Address offset: 0x84*/ 640 641 __IO u32 LCDC_LED_IDLE; /*!< LCDC LED I/F timing idle configuration register Address offset: 0x88*/ 642 __IO u32 RSVD4[1]; /*!< reserved space, 1 Dwords*/ 643 644 /*Image control*/ 645 __IO u32 LCDC_IMG_BASE_ADDR; /*!< LCDC Image base address register Address offset: 0x90*/ 646 } LCDC_TypeDef; 647 /** @} */ 648 649 /**************************************************************************//** 650 * @defgroup AMEBAD_CAPTOUCH 651 * @{ 652 * @brief AMEBAD_CAPTOUCH Register Declaration 653 *****************************************************************************/ 654 655 /** 656 * @brief CapTouch channel info 657 */ 658 typedef struct { 659 __IO uint32_t CTRL; /*!< ctrol register */ 660 __IO uint32_t ATHR; /*!< Absolute threshold */ 661 __IO uint32_t MBIAS; /*!< MBIAS current setting */ 662 __I uint32_t DATA; /*!< RAW Data */ 663 } CT_CH_TypeDef; 664 665 /** 666 * @brief CapTouch register info 667 */ 668 669 typedef struct 670 { 671 __IO uint32_t CT_CTRL; /*!< CAPTOUCH ctrl register, Address offset: 0x00 */ 672 __IO uint32_t CT_SP_CTRL; /*!< CAPTOUCH scan period ctrl register 0, Address offset: 0x04 */ 673 __IO uint32_t CT_ETC_CTRL; /*!< CAPTOUCH timer configure register 1, Address offset: 0x08 */ 674 675 __I uint32_t CT_SNR; /*!< CAPTOUCH SNR info register, Address offset: 0x0c */ 676 __IO uint32_t CT_MODE_CTRL; /*!< CAPTOUCH mode ctrl register, Address offset: 0x10 */ 677 __IO uint32_t CT_FIFO_STATUS; /*!< CAPTOUCH raw data fifo status register, Address offset: 0x14 */ 678 __IO uint32_t CT_FIFO; /*!< CAPTOUCH raw data fifo register, Address offset: 0x18 */ 679 680 __I uint32_t RSVD0; /*!< CAPTOUCH reserved register, Address offset: 0x1C */ 681 682 __IO uint32_t CT_IER; /*!< CAPTOUCH interrupt enable register, Address offset: 0x20 */ 683 __I uint32_t CT_ISR; /*!< CAPTOUCH interrupt status register, Address offset: 0x24*/ 684 __I uint32_t CT_ISR_RAW; /*!< CAPTOUCH Address offset: 0x28*/ 685 686 __I uint32_t RSVD1; /*!< CAPTOUCH reserved register, Address offset: 0x2C */ 687 688 __IO uint32_t CT_ICR_ALL; /*!< CAPTOUCH interrupt all clear register, Address offset: 0x30 */ 689 __IO uint32_t CT_ICR; /*!< CAPTOUCH interrupt clear register, Address offset: 0x34*/ 690 691 __I uint32_t RSVD2[50]; /*!< CAPTOUCH reserved register, Address offset: 0x38 */ 692 693 CT_CH_TypeDef CT_CH[5]; /*!< CAPTOUCH chanel register, Address offset: 0x100*/ 694 695 __I uint32_t RSVD3[172]; /*!< CAPTOUCH reserved register, Address offset: 0x150 */ 696 697 __IO uint32_t CT_ADC_REG0X_LPAD; /*!< CAPTOUCH ADC register, Address offset: 0x400 */ 698 __IO uint32_t CT_ADC_REG1X_LPAD; /*!< CAPTOUCH ADC register, Address offset: 0x404 */ 699 __IO uint32_t CT_ADC_REG0X_LPSD; /*!< CAPTOUCH ADC register, Address offset: 0x408 */ 700 __IO uint32_t CT_ADC_TIME; /*!< CAPTOUCH ADC register, Address offset: 0x40C */ 701 } CAPTOUCH_TypeDef; 702 /** @} */ 703 704 /**************************************************************************//** 705 * @defgroup AMEBAD_IR 706 * @{ 707 * @brief AMEBAD_IR Register Declaration 708 *****************************************************************************/ 709 typedef struct /*!< IR Structure */ 710 { 711 __IO u32 IR_CLK_DIV; /*!< IR clock DIV register, Address offset: 0x00 */ 712 __IO u32 IR_TX_CONFIG; /*!< IR TX config register, Address offset: 0x04 */ 713 __I u32 IR_TX_SR; /*!< IR TX status register, Address offset: 0x08 */ 714 __IO u32 IR_TX_COMPE_DIV; /*!< IR TX compensation register, Address offset: 0x0c */ 715 __IO u32 IR_TX_INT_CLR; /*!< IR TX interrupt clear register, Address offset: 0x10 */ 716 __O u32 IR_TX_FIFO; /*!< IR TX FIFO register, Address offset: 0x14 */ 717 __IO u32 IR_RX_CONFIG; /*!< IR RX config register, Address offset: 0x18 */ 718 __I u32 IR_RX_SR; /*!< IR RX status register, Address offset: 0x1c */ 719 __IO u32 IR_RX_INT_CLR; /*!< IR RX interrupt clear register, Address offset: 0x20 */ 720 __IO u32 IR_RX_CNT_INT_SEL; /*!< IR RX counter threshold register, Address offset: 0x24 */ 721 __I u32 IR_RX_FIFO; /*!< IR RX FIFO register Address offset: 0x28 */ 722 __I u32 IR_VERSION; /*!< IR HW version register, Address offset: 0x2c */ 723 } IR_TypeDef; 724 /** @} */ 725 726 /**************************************************************************//** 727 * @defgroup AMEBAD_QDEC 728 * @{ 729 * @brief AMEBAD_QDEC Register Declaration 730 *****************************************************************************/ 731 typedef struct 732 { 733 __IO uint32_t QDEC_CLK_CFG; /*!< QDEC Clock Configuration Register, Address offset: 0x00 */ 734 __IO uint32_t QDEC_CTRL; /*!< QDEC Control Register, Address offset: 0x04 */ 735 736 __IO uint32_t QDEC_MPC; /*!< QDEC Max Position Counter Register, Address offset: 0x08 */ 737 __IO uint32_t QDEC_RC; /*!< QDEC Rotation Compare Register, Address offset: 0x0c */ 738 __I uint32_t QDEC_PC; /*!< QDEC Position Counter Register, Address offset: 0x10 */ 739 __IO uint32_t QDEC_ISC; /*!< QDEC Index Signal Configuration Register,Address offset: 0x14 */ 740 741 __IO uint32_t QDEC_VCTRL; /*!< QDEC Velocity Control Register, Address offset: 0x18 */ 742 __I uint32_t QDEC_VC; /*!< QDEC Velocity Counter Register, Address offset: 0x1C */ 743 __I uint32_t QDEC_VCCAP; /*!< QDEC Velocity Counter Capture Register, Address offset: 0x20*/ 744 __I uint32_t QDEC_PCCAP; /*!< QDEC Position Counter Capture Register, Address offset: 0x24 */ 745 __IO uint32_t QDEC_VTRLD; /*!< QDEC Velocity Time Reload Register, Address offset: 0x28 */ 746 __IO uint32_t QDEC_VT; /*!< QDEC Velocity Timer Register, Address offset: 0x2C */ 747 __IO uint32_t QDEC_VCOMP; /*!< QDEC Velocity Compare Register, Address offset: 0x30 */ 748 749 __IO uint32_t DUMMY[2]; /*!< QDEC Velocity Rsvd, Address offset: 0x34 */ 750 751 __IO uint32_t QDEC_IMR; /*!< QDEC Interrupt Mask Register , Address offset: 0x3C */ 752 __IO uint32_t QDEC_ISR; /*!< QDEC raw Interrupt Status Register, Address offset: 0x40 */ 753 } QDEC_TypeDef; 754 /** @} */ 755 756 /**************************************************************************//** 757 * @defgroup AMEBAD_ADC 758 * @{ 759 * @brief AMEBAD_ADC Register Declaration 760 *****************************************************************************/ 761 typedef struct { 762 __IO uint32_t ADC_CONF; /*!< ADC configure register, Address offset: 0x00 */ 763 __IO uint32_t ADC_IN_TYPE; /*!< ADC channel input type register, Address offset: 0x04 */ 764 __IO uint32_t ADC_COMP_TH_CH[11]; /*!< ADC CH0~CH10 compare threshold register, Address offset: 0x08~0x30 */ 765 __IO uint32_t ADC_COMP_CTRL; /*!< ADC compare control register, Address offset: 0x34 */ 766 __I uint32_t ADC_COMP_STS; /*!< ADC compare status register, Address offset: 0x38 */ 767 __IO uint32_t ADC_CHSW_LIST[2]; /*!< ADC channel switch list register, Address offset: 0x3C~0x40 */ 768 __IO uint32_t ADC_RST_LIST; /*!< ADC reset channel list register, Address offset: 0x44 */ 769 __IO uint32_t ADC_AUTO_CSW_CTRL; /*!< ADC auto channel switch control register,Address offset: 0x48 */ 770 __IO uint32_t ADC_SW_TRIG; /*!< ADC software trigger register, Address offset: 0x4C */ 771 __I uint32_t ADC_LAST_CH; /*!< ADC last channel register, Address offset: 0x50 */ 772 __I uint32_t ADC_BUSY_STS; /*!< ADC busy status register, Address offset: 0x54 */ 773 __IO uint32_t ADC_INTR_CTRL; /*!< ADC interrupt control register, Address offset: 0x58 */ 774 __I uint32_t ADC_INTR_RAW_STS; /*!< ADC interrupt raw status register, Address offset: 0x5C */ 775 __IO uint32_t ADC_INTR_STS; /*!< ADC interrupt status register, Address offset: 0x60 */ 776 __IO uint32_t ADC_IT_CHNO_CON; /*!< ADC specified channel number register, Address offset: 0x64 */ 777 __IO uint32_t ADC_FULL_LVL; /*!< ADC FIFO full level register, Address offset: 0x68 */ 778 __IO uint32_t ADC_EXT_TRIG_TIMER_SEL;/*!< ADC external trigger timer selection register,Address offset: 0x6C */ 779 __IO uint32_t ADC_DATA_CH[11]; /*!< ADC CH0~CH10 data register, Address offset: 0x70~0x98 */ 780 __IO uint32_t ADC_DATA_GLOBAL; /*!< ADC global data register, Address offset: 0x9C */ 781 __IO uint32_t ADC_DMA_CON; /*!< ADC DMA control register, Address offset: 0xA0 */ 782 __IO uint32_t ADC_FLR; /*!< ADC FIFO entry number register, Address offset: 0xA4 */ 783 __IO uint32_t ADC_CLR_FIFO; /*!< ADC clear FIFO register, Address offset: 0xA8 */ 784 __IO uint32_t ADC_CLK_DIV; /*!< ADC clock divider register, Address offset: 0xAC */ 785 __IO uint32_t ADC_DELAY_CNT; /*!< ADC channel switch delay register, Address offset: 0xB0 */ 786 __IO uint32_t ADC_PWR_CTRL; /*!< ADC power control register, Address offset: 0xB4 */ 787 } ADC_TypeDef; 788 789 /** @} */ 790 791 /**************************************************************************//** 792 * @defgroup AMEBAD_COMPARE 793 * @{ 794 * @brief AMEBAD_COMPARE Register Declaration 795 *****************************************************************************/ 796 typedef struct { 797 __IO uint32_t COMP_REF_CH[4]; /*!< COMPARE CH0~3 reference voltage register , Address offset: 0x00~0x0C */ 798 __IO uint32_t COMP_INTR_CTRL; /*!< COMPARE interrupt control register, Address offset: 0x10 */ 799 __IO uint32_t COMP_WK_STS; /*!< COMPARE wakeup ADC/SYS status register, Address offset: 0x14 */ 800 __I uint32_t COMP_WK_RAW_STS; /*!< COMPARE wakeup ADC/SYS status raw register, Address offset: 0x18 */ 801 __IO uint32_t COMP_CHSW_LIST; /*!< COMPARE channel switch list register, Address offset: 0x1C */ 802 __IO uint32_t COMP_LAST_CH; /*!< COMPARE last channel register, Address offset: 0x20 */ 803 __I uint32_t COMP_BUSY_STS; /*!< COMPARE busy status register, Address offset: 0x24 */ 804 __I uint32_t COMP_CH_STS; /*!< COMPARE channel status register, Address offset: 0x28 */ 805 __IO uint32_t COMP_AUTO_SHUT; /*!< COMPARE automatic shut register, Address offset: 0x2C */ 806 __IO uint32_t COMP_EXT_TRIG_CTRL; /*!< COMPARE ext trigger control register, Address offset: 0x30 */ 807 __IO uint32_t COMP_EXT_TRIG_TIMER_SEL; /*!< COMPARE ext trigger timer select register, Address offset: 0x34 */ 808 __IO uint32_t COMP_RST_LIST; /*!< COMPARE reset channel list register, Address offset: 0x38 */ 809 __IO uint32_t COMP_AUTOSW_EN; /*!< COMPARE automatic channel switch enable register, Address offset: 0x3C */ 810 __IO uint32_t COMP_EN_TRIG; /*!< COMPARE enable trigger register, Address offset: 0x40 */ 811 __IO uint32_t COMP_EXT_WK_SHUT_CTRL; /*!< COMPARE ext wake shut count register, Address offset: 0x44 */ 812 __IO uint32_t COMP_ANALOG; /*!< COMPARE analog register, Address offset: 0x48 */ 813 } CMP_TypeDef; 814 815 /** @} */ 816 817 /**************************************************************************//** 818 * @defgroup AMEBAD_I2C 819 * @{ 820 * @brief AMEBAD_I2C Register Declaration 821 *****************************************************************************/ 822 typedef struct 823 { 824 __IO uint32_t IC_CON; /*!< I2C control register, Address offset: 0x00 */ 825 __IO uint32_t IC_TAR; /*!< I2C target address register, Address offset: 0x04 */ 826 __IO uint32_t IC_SAR; /*!< I2C slave0 address register, Address offset: 0x08 */ 827 __IO uint32_t IC_HS_MADDR; /*!< I2C HS master mode code address register, Address offset: 0x0C */ 828 829 __IO uint32_t IC_DATA_CMD; /*!< I2C rx/tx data buffer and command register, Address offset: 0x10 */ 830 __IO uint32_t IC_SS_SCL_HCNT; /*!< I2C standard speed clock SCL high count register, Address offset: 0x14 */ 831 __IO uint32_t IC_SS_SCL_LCNT; /*!< I2C standard speed clock SCL low count register, Address offset: 0x18 */ 832 __IO uint32_t IC_FS_SCL_HCNT; /*!< I2C fast speed clock SCL high count register, Address offset: 0x1C */ 833 834 __IO uint32_t IC_FS_SCL_LCNT; /*!< I2C fast speed clock SCL low count register, Address offset: 0x20 */ 835 __IO uint32_t IC_HS_SCL_HCNT; /*!< I2C high speed clock SCL high count register, Address offset: 0x24 */ 836 __IO uint32_t IC_HS_SCL_LCNT; /*!< I2C high speed clock SCL low count register, Address offset: 0x28 */ 837 __I uint32_t IC_INTR_STAT; /*!< I2C interrupt status register, Address offset: 0x2C */ 838 839 __IO uint32_t IC_INTR_MASK; /*!< I2C interrupt mask register, Address offset: 0x30 */ 840 __I uint32_t IC_RAW_INTR_STAT; /*!< I2C raw interrupt status register, Address offset: 0x34 */ 841 __IO uint32_t IC_RX_TL; /*!< I2C receive FIFO threshold register, Address offset: 0x38 */ 842 __IO uint32_t IC_TX_TL; /*!< I2C transmit FIFO threshold register, Address offset: 0x3C */ 843 844 __I uint32_t IC_CLR_INTR; /*!< I2C clear combined and individual interrupts register, Address offset: 0x40 */ 845 __I uint32_t IC_CLR_RX_UNDER; /*!< I2C clear RX_UNDER interrupt register, Address offset: 0x44 */ 846 __I uint32_t IC_CLR_RX_OVER; /*!< I2C clear RX_OVER interrupt register, Address offset: 0x48 */ 847 __I uint32_t IC_CLR_TX_OVER; /*!< I2C clear TX_OVER interrupt register, Address offset: 0x4C */ 848 849 __I uint32_t IC_CLR_RD_REQ; /*!< I2C clear RD_REQ interrupt register, Address offset: 0x50 */ 850 __I uint32_t IC_CLR_TX_ABRT; /*!< I2C clear TX_ABRT interrupt register, Address offset: 0x54 */ 851 __I uint32_t IC_CLR_RX_DONE; /*!< I2C clear RX_DONE interrupt register, Address offset: 0x58 */ 852 __I uint32_t IC_CLR_ACTIVITY; /*!< I2C clear ACTIVITY interrupt register, Address offset: 0x5C */ 853 854 __I uint32_t IC_CLR_STOP_DET; /*!< I2C clear STOP_DET interrupt register, Address offset: 0x60 */ 855 __I uint32_t IC_CLR_START_DET; /*!< I2C clear START_DET interrupt register, Address offset: 0x64 */ 856 __I uint32_t IC_CLR_GEN_CALL; /*!< I2C clear GEN_CALL interrupt register, Address offset: 0x68 */ 857 __IO uint32_t IC_ENABLE; /*!< I2C enable register, Address offset: 0x6C */ 858 859 __I uint32_t IC_STATUS; /*!< I2C status register, Address offset: 0x70 */ 860 __I uint32_t IC_TXFLR; /*!< I2C transmit FIFO level register, Address offset: 0x74 */ 861 __I uint32_t IC_RXFLR; /*!< I2C receive FIFO level register, Address offset: 0x78 */ 862 __IO uint32_t IC_SDA_HOLD; /*!< I2C SDA hold time length register, Address offset: 0x7C */ 863 864 __I uint32_t IC_TX_ABRT_SOURCE; /*!< I2C transmit abort status register, Address offset: 0x80 */ 865 __IO uint32_t IC_SLV_DATA_NACK_ONLY; /*!< I2C generate SLV_DATA_NACK register, Address offset: 0x84 */ 866 __IO uint32_t IC_DMA_CR; /*!< I2C DMA Control Register for transmit and receive handshaking interface, Address offset: 0x88 */ 867 __IO uint32_t IC_DMA_TDLR; /*!< I2C DMA transmit data level register, Address offset: 0x8C */ 868 869 __IO uint32_t IC_DMA_RDLR; /*!< I2C DMA receive data level register, Address offset: 0x90 */ 870 __IO uint32_t IC_SDA_SETUP; /*!< I2C SDA setup register, Address offset: 0x94 */ 871 __IO uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK general call register, Address offset: 0x98 */ 872 __IO uint32_t IC_ENABLE_STATUS; /*!< I2C enable status register, Address offset: 0x9C */ 873 874 __IO uint32_t IC_DMA_CMD; /*!< I2C DMA command register, Address offset: 0xA0 */ 875 __IO uint32_t IC_DMA_DAT_LEN; /*!< I2C DMA Mode Transfer Data Length Register, Address offset: 0xA4 */ 876 __IO uint32_t IC_DMA_MOD; /*!< I2C DMA mode register, Address offset: 0xA8 */ 877 __IO uint32_t IC_SLEEP; /*!< I2C sleep control register, Address offset: 0xAC */ 878 879 __IO uint32_t IC_RSVD1[4]; /*!< I2C reserved field, Address offset: 0xB0 */ 880 __I uint32_t IC_RSVD2[4]; /*!< I2C reserved field, Address offset: 0xC0 */ 881 __I uint32_t IC_RSVD3[4]; /*!< I2C reserved field, Address offset: 0xD0 */ 882 883 __I uint32_t IC_RSVD4; /*!< I2C reserved field, Address offset: 0xE0 */ 884 __I uint32_t IC_CLR_ADDR_MATCH; /*!< I2C clear ADDR_MATCH interrupt register, Address offset: 0xE4 */ 885 __I uint32_t IC_CLR_DMA_I2C_DONE; /*!< I2C clear DMA_I2C_DONE interrupt register, Address offset: 0xE8 */ 886 __IO uint32_t IC_FILTER; /*!< I2C filter register, Address offset: 0xEC */ 887 888 __I uint32_t IC_RSVD5; /*!< I2C reserved field, Address offset: 0xF0 */ 889 __IO uint32_t IC_SAR1; /*!< I2C slave1 address register, not support in amebaD Address offset: 0xF4 */ 890 __IO uint32_t IC_DATA_S1; /*!< I2C slave1 rx/tx data buffer register, not support in amebaD Address offset: 0xF8 */ 891 __I uint32_t IC_COMP_VERSION; /*!< I2C component version ID register, Address offset: 0xFC */ 892 } I2C_TypeDef; 893 /** @} */ 894 895 /**************************************************************************//** 896 * @defgroup AMEBAD_I2S 897 * @{ 898 * @brief AMEBAD_I2S Register Declaration 899 *****************************************************************************/ 900 typedef struct 901 { 902 __IO uint32_t IS_CTL; /*!< I2S control register, Address offset: 0x00 */ 903 __IO uint32_t IS_TX_PAGE_PTR; /*!< I2S TX page pointer register, Address offset: 0x04 */ 904 __IO uint32_t IS_RX_PAGE_PTR; /*!< I2S RX page pointer register, Address offset: 0x08 */ 905 __IO uint32_t IS_SETTING; /*!< I2S page size and sample rate setting register, Address offset: 0x0c */ 906 907 __IO uint32_t IS_TX_MASK_INT; /*!< I2S TX interrupt enable register, Address offset: 0x10 */ 908 __IO uint32_t IS_TX_STATUS_INT; /*!< I2S TX interrupt status register, Address offset: 0x14 */ 909 __IO uint32_t IS_RX_MASK_INT; /*!< I2S RX interrupt enable register, Address offset: 0x18 */ 910 __IO uint32_t IS_RX_STATUS_INT; /*!< I2S RX interrupt status register, Address offset: 0x1C */ 911 912 __IO uint32_t IS_TX_PAGE_OWN[4]; /*!< I2S TX page own bit register, Address offset: 0x20-0x2c */ 913 __IO uint32_t IS_RX_PAGE_OWN[4]; /*!< I2S RX page own bit register, Address offset: 0x30-0x3c */ 914 __I uint32_t IS_VERSION_ID; /*!< I2S RX page own bit register, Address offset: 0x40 */ 915 } I2S_TypeDef; 916 /** @} */ 917 918 /**************************************************************************//** 919 * @defgroup AMEBAD_AUDIO_SI 920 * @{ 921 * @brief AMEBAD_AUDIO_SI Register Declaration 922 *****************************************************************************/ 923 typedef struct 924 { 925 __IO uint32_t SI_CTRLR; /*!< SI control register, Address offset: 0x00 */ 926 __IO uint32_t SI_CLK_EN; /*!< SI TX page pointer register, Address offset: 0x04 */ 927 } AUDIO_SI_TypeDef; 928 /** @} */ 929 930 /**************************************************************************//** 931 * @defgroup AMEBAD_AUDIO_SPORT 932 * @{ 933 * @brief AMEBAD_AUDIO_SPORT Register Declaration 934 *****************************************************************************/ 935 typedef struct 936 { 937 __O uint32_t SP_TX_DR; /*!< SPORT TX data register, Address offset: 0x00 */ 938 __IO uint32_t SP_CTRLR0; /*!< SPORT control 0 register, Address offset: 0x04 */ 939 __IO uint32_t SP_CTRLR1; /*!< SPORT control 1 register, Address offset: 0x08 */ 940 __IO uint32_t SP_DSP_INT_CR; /*!< SPORT DSP interrupt clear register, Address offset: 0x0C */ 941 __I uint32_t SP_RX_DR; /*!< SPORT RX data register, Address offset: 0x10 */ 942 __I uint32_t SP_FIFO_SR; /*!< SPORT FIFO status register, Address offset: 0x14 */ 943 __IO uint32_t SP_ERROR_CNT_SR; /*!< SPORT error counter register, Address offset: 0x18 */ 944 __IO uint32_t SP_CLK_DIV; /*!< SPORT clock divide register, Address offset: 0x1C */ 945 } AUDIO_SPORT_TypeDef; 946 /** @} */ 947 948 /**************************************************************************//** 949 * @defgroup AMEBAD_TIMER 950 * @{ 951 * @brief AMEBAD_TIMER Register Declaration 952 * @note TIM1 have 6 CCR registers: bit[15:0] is CCR, bit[31:24] is CCMR 953 * @note TIM3 have 1 CCR registesr: bit[15:0] is CCR, bit[31:24] is CCMR 954 * @note TIM5-8 dont have CCR register 955 *****************************************************************************/ 956 /** 957 * @brief RTK TIM CCR 958 */ 959 typedef struct { 960 __IO uint16_t CCRx; /*!< TIM capture/compare register */ 961 __IO uint8_t RSVD; /*!< TIM capture/compare rsvd register */ 962 __IO uint8_t CCMRx; /*!< TIM capture/compare register */ 963 } RTIM_CCR_TypeDef; 964 965 /** 966 * @brief RTK TIM 967 */ 968 typedef struct { 969 __IO uint32_t EN; /*!< TIM Enable register, Address offset: 0x00 */ 970 __IO uint32_t CR; /*!< TIM control register, Address offset: 0x04 */ 971 __IO uint32_t DIER; /*!< TIM interrupt enable register, Address offset: 0x08 */ 972 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x0C */ 973 __O uint32_t EGR; /*!< TIM event generation register, Address offset: 0x10 */ 974 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x14 */ 975 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x18 */ 976 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x1C */ 977 978 __IO uint32_t CCMRx[18]; /*!< TIM capture/compare registers Address offset: 0x20~0x64*/ 979 } RTIM_TypeDef; 980 /** @} */ 981 982 /**************************************************************************//** 983 * @defgroup AMEBAD_RTC 984 * @{ 985 * @brief AMEBAD_RTC Register Declaration 986 *****************************************************************************/ 987 typedef struct { 988 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 989 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x04 */ 990 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x08 */ 991 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x0C*/ 992 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x10 */ 993 __IO uint32_t ALMR1L; /*!< RTC alarm register1, Address offset: 0x14 */ 994 __IO uint32_t ALMR1H; /*!< RTC alarm register2, Address offset: 0x18 */ 995 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x1C */ 996 __IO uint32_t CLKACALR; /*!< RTC 32k auto calibration register, Address offset: 0x20 */ 997 } RTC_TypeDef; 998 /** @} */ 999 1000 /**************************************************************************//** 1001 * @defgroup AMEBAD_PINMUX 1002 * @{ 1003 * @brief AMEBAD_PINMUX Register Declaration 1004 *****************************************************************************/ 1005 typedef struct { 1006 __IO uint32_t PADCTR[64]; /*!< Pad control register */ 1007 } PINMUX_TypeDef; 1008 /** @} */ 1009 1010 /**************************************************************************//** 1011 * @defgroup AMEBAD_GPIO 1012 * @{ 1013 * @brief AMEBAD_GPIO Register Declaration 1014 *****************************************************************************/ 1015 /** 1016 * @brief GPIO port 1017 */ 1018 typedef struct { 1019 __IO uint32_t DR; /*!< data register */ 1020 __IO uint32_t DDR; /*!< data direction */ 1021 __IO uint32_t CTRL; /*!< data source control, we should keep it as default: data source from software */ 1022 } GPIO_Port_TypeDef; 1023 1024 /** 1025 * @brief General purpose input and output. (GPIO) 1026 */ 1027 typedef struct { 1028 GPIO_Port_TypeDef PORT[4]; /*!< GPIO IP have 4 ports, Address offset: 0x00-0x2C */ 1029 1030 __IO uint32_t INT_EN; /*!< GPIO interrupt enable register, Address offset: 0x30 */ 1031 __IO uint32_t INT_MASK; /*!< GPIO interrupt mask register, Address offset: 0x34 */ 1032 __IO uint32_t INT_TYPE; /*!< GPIO interrupt type(level/edge) register, Address offset: 0x38 */ 1033 __IO uint32_t INT_POLARITY; /*!< GPIO interrupt polarity(Active low/high) register, Address offset: 0x3C */ 1034 __IO uint32_t INT_STATUS; /*!< GPIO interrupt status register, Address offset: 0x40 */ 1035 __IO uint32_t INT_RAWSTATUS; /*!< GPIO interrupt status without mask register, Address offset: 0x44 */ 1036 __IO uint32_t DEBOUNCE; /*!< GPIO interrupt signal debounce register, Address offset: 0x48 */ 1037 __IO uint32_t PORTA_EOI; /*!< GPIO clear interrupt register, Address offset: 0x4C */ 1038 1039 __IO uint32_t EXT_PORT[4]; /*!< GPIO IN read or OUT read back register, Address offset: 0x50-0x5C */ 1040 1041 __IO uint32_t LSSYNC; /*!< GPIO level-sensitive synchronization enable register, Address offset: 0x60 */ 1042 __IO uint32_t IDCODE; /*!< GPIO ID code register, Address offset: 0x64 */ 1043 __IO uint32_t INT_BOTHEDGE; /*!< GPIO Both Edge Interrupt, Address offset: 0x68 */ 1044 __IO uint32_t VERIDCODE; /*!< GPIO component Version register, Address offset: 0x6C */ 1045 __IO uint32_t CONFIG2; /*!< GPIO configuration Register 2, Address offset: 0x70 */ 1046 __IO uint32_t CONFIG1; /*!< GPIO configuration Register 1, Address offset: 0x74 */ 1047 } GPIO_TypeDef; 1048 1049 /** @} */ 1050 1051 /**************************************************************************//** 1052 * @defgroup AMEBAD_IPSEC 1053 * @{ 1054 * @brief AMEBAD_IPSEC Register Declaration 1055 *****************************************************************************/ 1056 typedef struct { 1057 __IO uint32_t SDSR; /*!< IPsec source descriptor fifo status register, Address offset: 0x0000 */ 1058 __IO uint32_t SDFW; /*!< IPsec source descriptor first word, Address offset: 0x0004 */ 1059 __IO uint32_t SDSW; /*!< IPsec source descriptor second word, Address offset: 0x0008 */ 1060 uint32_t RSVD0; /*!< Reserved, 0x000C*/ 1061 __IO uint32_t RST_ISR_CON; /*!< IPsec reset and interrupt register, Address offset: 0x0010 */ 1062 __IO uint32_t IMR; /*!< IPsec interrupt mask register, Address offset: 0x0014 */ 1063 __IO uint32_t DEBUG; /*!< IPsec debug register, Address offset: 0x0018 */ 1064 __IO uint32_t ERR_STAT; /*!< IPsec interrupt error status register, Address offset: 0x001C */ 1065 __I uint32_t A2EO_SUM; /*!< IPsec a2eo sum register, Address offset: 0x0020*/ 1066 __I uint32_t ENL_SUM; /*!< IPsec encryption length sum register, Address offset: 0x0024 */ 1067 __I uint32_t APL_SUM; /*!< IPsec authentication padding length sum register, Address offset: 0x0028*/ 1068 __I uint32_t EPL_SUM; /*!< IPsec encryption padding length sum register, Address offset: 0x002C */ 1069 __IO uint32_t SWAP_BURST; /*!< IPsec swap/burst register, Address offset: 0x0030 */ 1070 uint32_t RSVD1[3]; /*!< Reserved, 0x0034 -0x003C*/ 1071 __I uint32_t ENG_DBG; /*!< IPsec engine debug register, Address offset: 0x0040*/ 1072 __I uint32_t DMA_LX_DBG; /*!< IPsec lexra bus debug register, Address offset: 0x0044 */ 1073 __I uint32_t DMA_RX_DBG; /*!< IPsec dma rx debug register, Address offset: 0x0048*/ 1074 __I uint32_t DMA_TX_DBG; /*!< IPsec dma tx debug register, Address offset: 0x004C */ 1075 __I uint32_t STA_SDES_CFG; /*!<IPsec source descriptor configure debug register, Address offset: 0x0050*/ 1076 __I uint32_t STA_SDES_PTR; /*!< IPsec source descriptor pointer debug register, Address offset: 0x0054 */ 1077 __I uint32_t STA_SDES_CMD1; /*!< IPsec source descriptor command#1 debug register, Address offset: 0x0058*/ 1078 __I uint32_t STA_SDES_CMD2; /*!< IPsec source descriptor command#2 debug register, Address offset: 0x005C */ 1079 __I uint32_t STA_SDES_CMD3; /*!< IPsec source descriptor command#3 debug register, Address offset: 0x0060*/ 1080 __I uint32_t STA_DDES_CFG; /*!< IPsec destination descriptor configure debug register, Address offset: 0x0064 */ 1081 __I uint32_t STA_DDES_PTR; /*!< IPsec destination descriptor pointer debug register, Address offset: 0x0068*/ 1082 uint32_t RSVD2[3]; /*!< Reserved, 0x006C -0x0074*/ 1083 __IO uint32_t CFG_SSET_ADDR_L_LIMIT; /*!< Source command setting low boundary address register, Address offset: 0x0078 */ 1084 __IO uint32_t CFG_SSET_ADDR_H_LIMIT; /*!< Source command setting high boundary address register, Address offset: 0x007C */ 1085 __IO uint32_t CFG_SDATA_ADDR_L_LIMIT; /*!< IPsec source data low boundary address register, Address offset: 0x0080 */ 1086 __IO uint32_t CFG_SDATA_ADDR_H_LIMIT;/*!< IPsec source data high boundary address register, Address offset: 0x0084 */ 1087 uint32_t RSVD3[2]; /*!< Reserved, 0x0088 -0x008C*/ 1088 __IO uint32_t CFG_DDATA_ADDR_L_LIMIT;/*!< IPsec destination data low boundary address register, Address offset: 0x0090 */ 1089 __IO uint32_t CFG_DDATA_ADDR_H_LIMIT;/*!< IPsec destination data high boundary address register, Address offset: 0x0094 */ 1090 uint32_t RSVD4[2]; /*!< Reserved, 0x0098 -0x009C*/ 1091 __O uint32_t SK0_R0; /*!< IPsec secure key 0 (bit 224-255) register, Address offset: 0x00A0 */ 1092 __O uint32_t SK0_R1; /*!< IPsec secure key 0 (bit 192-223) register, Address offset: 0x00A4 */ 1093 __O uint32_t SK0_R2; /*!< IPsec secure key 0 (bit 160-191) register, Address offset: 0x00A8 */ 1094 __O uint32_t SK0_R3; /*!< IPsec secure key 0 (bit 128-159) register, Address offset: 0x00AC */ 1095 __O uint32_t SK0_R4; /*!< IPsec secure key 0 (bit 96-127) register, Address offset: 0x00B0 */ 1096 __O uint32_t SK0_R5; /*!< IPsec secure key 0 (bit 64-95) register, Address offset: 0x00B4 */ 1097 __O uint32_t SK0_R6; /*!< IPsec secure key 0 (bit 32-63) register, Address offset: 0x00B8 */ 1098 __O uint32_t SK0_R7; /*!< IPsec secure key 0 (bit 0-31) register, Address offset: 0x00BC */ 1099 __O uint32_t SK1_R0; /*!< IPsec secure key 1 (bit 224-255) register, Address offset: 0x00C0 */ 1100 __O uint32_t SK1_R1; /*!< IPsec secure key 1 (bit 192-223) register, Address offset: 0x00C4 */ 1101 __O uint32_t SK1_R2; /*!< IPsec secure key 1 (bit 160-191) register, Address offset: 0x00C8 */ 1102 __O uint32_t SK1_R3; /*!< IPsec secure key 1 (bit 128-159) register, Address offset: 0x00CC */ 1103 __O uint32_t SK1_R4; /*!< IPsec secure key 1 (bit 96-127) register, Address offset: 0x00D0 */ 1104 __O uint32_t SK1_R5; /*!< IPsec secure key 1 (bit 64-95) register, Address offset: 0x00D4 */ 1105 __O uint32_t SK1_R6; /*!< IPsec secure key 1 (bit 32-63) register, Address offset: 0x00D8 */ 1106 __O uint32_t SK1_R7; /*!< IPsec secure key 1 (bit 0-31) register, Address offset: 0x00DC */ 1107 __O uint32_t SK2_R0; /*!< IPsec secure key 2 (bit 224-255) register, Address offset: 0x00E0 */ 1108 __O uint32_t SK2_R1; /*!< IPsec secure key 2 (bit 192-223) register, Address offset: 0x00E4 */ 1109 __O uint32_t SK2_R2; /*!< IPsec secure key 2 (bit 160-191) register, Address offset: 0x00E8 */ 1110 __O uint32_t SK2_R3; /*!< IPsec secure key 2 (bit 128-159) register, Address offset: 0x00EC */ 1111 __O uint32_t SK2_R4; /*!< IPsec secure key 2 (bit 96-127) register, Address offset: 0x00F0 */ 1112 __O uint32_t SK2_R5; /*!< IPsec secure key 2 (bit 64-95) register, Address offset: 0x00F4 */ 1113 __O uint32_t SK2_R6; /*!< IPsec secure key 2 (bit 32-63) register, Address offset: 0x00F8 */ 1114 __O uint32_t SK2_R7; /*!< IPsec secure key 2 (bit 0-31) register, Address offset: 0x00FC */ 1115 uint32_t CRC_RSVD[10]; /*!< CRC Reserved, 0x0100 -0x0124*/ 1116 uint32_t RSVD5[472]; /*!< Reserved, 0x0128 -0x0884*/ 1117 __I uint32_t DBG_VERSION; /*!< IPsec version register, Address offset: 0x0888 */ 1118 uint32_t RSVD6[477]; /*!< Reserved, 0x088C -0x0FFC*/ 1119 __IO uint32_t DDSR; /*!< IPsec destination descriptor fifo status register, Address offset: 0x1000 */ 1120 __IO uint32_t DDFW; /*!< IPsec destination descriptor first word, Address offset: 0x1004 */ 1121 __IO uint32_t DDSW; /*!< IPsec destination descriptor second word, Address offset: 0x1008 */ 1122 __IO uint32_t DESC_PKT_CONF; /*!< IPsec descriptor packet setting register, Address offset: 0x100C */ 1123 __I uint32_t DBG_SD; /*!< IPsec source descriptor data debug register, Address offset: 0x1010 */ 1124 __I uint32_t DBG_DD; /*!< IPsec destination descriptor data debug register, Address offset: 0x1014 */ 1125 } IPSEC_TypeDef; 1126 /** @} */ 1127 1128 /**************************************************************************//** 1129 * @defgroup AMEBAD_CRC 1130 * @{ 1131 * @brief AMEBAD_CRC Register Declaration 1132 *****************************************************************************/ 1133 typedef struct { 1134 __O uint32_t CRC_RST; /*!< CRC reset register, Address offset: 0x0000 */ 1135 __IO uint32_t CRC_OP; /*!< CRC operation register, Address offset: 0x0004 */ 1136 __IO uint32_t CRC_POLY; /*!< CRC polynomia register, Address offset: 0x0008 */ 1137 __IO uint32_t CRC_IV; /*!< CRC initial value register, Address offset: 0x000C */ 1138 __IO uint32_t CRC_OXOR; /*!< CRC xor output register, Address offset: 0x0010 */ 1139 __IO uint32_t CRC_DATA; /*!< CRC data register, Address offset: 0x0014 */ 1140 __IO uint32_t CRC_STAT; /*!< CRC status register, Address offset: 0x0018 */ 1141 __I uint32_t CRC_RESULT; /*!< CRC result register, Address offset: 0x001C */ 1142 __I uint32_t CRC_CNT; /*!< CRC count register, Address offset: 0x0020 */ 1143 __I uint32_t CRC_DMA_RX_DBG; /*!< CRC dma rx debug register, Address offset: 0x0024 */ 1144 } CRC_TypeDef; 1145 /** @} */ 1146 1147 /**************************************************************************//** 1148 * @defgroup AMEBAD_KEYSCAN 1149 * @{ 1150 * @brief AMEBAD_KEYSCAN Register Declaration 1151 *****************************************************************************/ 1152 typedef struct 1153 { 1154 __IO uint32_t KS_CLK_DIV; /*!< KEYSCAN clock divide register, Address offset: 0x00 */ 1155 __IO uint32_t KS_TIM_CFG0; /*!< KEYSCAN timer configure register 0, Address offset: 0x04 */ 1156 __IO uint32_t KS_TIM_CFG1; /*!< KEYSCAN timer configure register 1, Address offset: 0x08 */ 1157 __IO uint32_t KS_CTRL; /*!< KEYSCAN control register, Address offset: 0x0c */ 1158 1159 __IO uint32_t KS_FIFO_CFG; /*!< KEYSCAN FIFO configure register, Address offset: 0x10 */ 1160 __IO uint32_t KS_COL_CFG; /*!< KEYSCAN column configure register, Address offset: 0x14 */ 1161 __IO uint32_t KS_ROW_CFG; /*!< KEYSCAN row configure register, Address offset: 0x18 */ 1162 __I uint32_t KS_DATA_NUM; /*!< KEYSCAN FIFO data number register, Address offset: 0x1C */ 1163 __I uint32_t KS_DATA_ENTRY; /*!< KEYSCAN event code register, Address offset: 0x20*/ 1164 1165 __IO uint32_t KS_IMR; /*!< KEYSCAN interrupt mask register, Address offset: 0x24 */ 1166 __IO uint32_t KS_ICR; /*!< KEYSCAN interrupt clear register, Address offset: 0x28 */ 1167 __I uint32_t KS_ISR; /*!< KEYSCAN interrupt status register, Address offset: 0x2C */ 1168 __I uint32_t KS_ISR_RAW; /*!< KEYSCAN raw interrupt status register, Address offset: 0x30 */ 1169 } KEYSCAN_TypeDef; 1170 /** @} */ 1171 1172 /**************************************************************************//** 1173 * @defgroup AMEBAD_SGPIO 1174 * @{ 1175 * @brief AMEBAD_SGPIO Register Declaration 1176 *****************************************************************************/ 1177 typedef struct 1178 { 1179 /*RX Timer Control Registers*/ 1180 __IO uint32_t SGPIO_RXTMR_CTRL; /*!< SGPIO RX Timer Control Register, Address offset: 0x00 */ 1181 __IO uint32_t SGPIO_RXPRVAL; /*!< SGPIO RX Maximum Prescale Register, Address offset: 0x04 */ 1182 __IO uint32_t SGPIO_RXPRTC; /*!< SGPIO RX Timer Prescale Register, Address offset: 0x08 */ 1183 __IO uint32_t SGPIO_RXTC; /*!< SGPIO RX Timer Counter Register, Address offset: 0x0C */ 1184 __IO uint32_t SGPIO_RXMC_CTRL; /*!< SGPIO RX Match Control Register, Address offset: 0x10 */ 1185 __IO uint32_t SGPIO_RXMR0; /*!< SGPIO RX Match Register 0, Address offset: 0x14 */ 1186 __IO uint32_t SGPIO_RXMR1; /*!< SGPIO RX Match Register 1, Address offset: 0x18 */ 1187 __IO uint32_t SGPIO_RXMR2; /*!< SGPIO RX Match Register 2, Address offset: 0x1C */ 1188 1189 /*Capture Function Control Registers*/ 1190 __IO uint32_t SGPIO_CAP_CTRL; /*!< SGPIO Capture Control Register, Address offset: 0x20 */ 1191 __IO uint32_t SGPIO_CAPR; /*!< SGPIO Capture Register, Address offset: 0x24 */ 1192 1193 /*Multiple Timer Control Registers*/ 1194 __IO uint32_t SGPIO_MULTMR_CTRL; /*!< SGPIO Multiple Timer Control Register, Address offset: 0x28 */ 1195 __IO uint32_t SGPIO_MULPRVAL; /*!< SGPIO Multiple Maximum Prescale Register, Address offset: 0x2C */ 1196 __IO uint32_t SGPIO_MULPRTC; /*!< SGPIO Multiple Timer Prescale Register, Address offset: 0x30 */ 1197 __IO uint32_t SGPIO_MULTC; /*!< SGPIO Multiple Timer Counter Register, Address offset: 0x34 */ 1198 __IO uint32_t SGPIO_MULMC_CTRL; /*!< SGPIO Multiple Match Control Register, Address offset: 0x38 */ 1199 __IO uint32_t SGPIO_MULMR01GP0; /*!< SGPIO Multiple Match Register 0 & 1 For Group 0, Address offset: 0x3C */ 1200 __IO uint32_t SGPIO_MULMR23GP0; /*!< SGPIO Multiple Match Register 2 & 3 For Group 0, Address offset: 0x40 */ 1201 __IO uint32_t SGPIO_MULMR01GP1; /*!< SGPIO Multiple Match Register 0 & 1 For Group 1, Address offset: 0x44 */ 1202 __IO uint32_t SGPIO_MULMR23GP1; /*!< SGPIO Multiple Match Register 2 & 3 For Group 1, Address offset: 0x48 */ 1203 __IO uint32_t SGPIO_MUL_MCNT; /*!< SGPIO Multiple Match Counter Register, Address offset: 0x4C */ 1204 1205 /*Data and Interrupt control Registers*/ 1206 __IO uint32_t SGPIO_MULEMR; /*!< SGPIO External Match Control Register, Address offset: 0x50 */ 1207 __IO uint32_t SGPIO_DATA_CTRL; /*!< SGPIO Data Control Register, Address offset: 0x54 */ 1208 __IO uint32_t SGPIO_RXDATA; /*!< SGPIO RX Data Register, Address offset: 0x58 */ 1209 __IO uint32_t SGPIO_RXDATA_DP; /*!< SGPIO RX Data Duplicate Register, Address offset: 0x5C */ 1210 __IO uint32_t SGPIO_RXPOSR; /*!< SGPIO RX Position Register, Address offset: 0x60 */ 1211 __IO uint32_t SGPIO_RXDATAMASK; /*!< SGPIO RX Data Mask Register, Address offset: 0x64 */ 1212 __IO uint32_t SGPIO_MULDATA; /*!< SGPIO Multiple Data Register, Address offset: 0x68 */ 1213 __IO uint32_t SGPIO_MULDATA_DP; /*!< SGPIO Multiple Data Duplicate Register, Address offset: 0x6C */ 1214 __IO uint32_t SGPIO_MULPOSR; /*!< SGPIO Multiple Position Register, Address offset: 0x70 */ 1215 __IO uint32_t SGPIO_MULFDATA; /*!< SGPIO Multiple FIFO Data Register, Address offset: 0x74 */ 1216 __IO uint32_t SGPIO_ISR; /*!< SGPIO Interrupt Status Register, Address offset: 0x78 */ 1217 __IO uint32_t SGPIO_GF; /*!< SGPIO Glitch Filter Register, Address offset: 0x7C */ 1218 __IO uint32_t SGPIO_OUTPUT; /*!< SGPIO Output Register, Address offset: 0x80 */ 1219 __IO uint32_t SGPIO_IMR; /*!< SGPIO Interrupt Mask Register, Address offset: 0x84 */ 1220 } SGPIO_TypeDef; 1221 /** @} */ 1222 1223 /**************************************************************************//** 1224 * @defgroup AMEBAD_PSRAM 1225 * @{ 1226 * @brief AMEBAD_PSRAM Register Declaration 1227 *****************************************************************************/ 1228 typedef struct 1229 { 1230 __IO uint32_t CCR; /*!< PSRAM Configuration control register, Address offset: 0x000 */ 1231 __IO uint32_t DCR; /*!< PSRAM Device Configuration control register, Address offset: 0x004 */ 1232 __IO uint32_t IOCR0; /*!< PSRAM I/O Configuration control register0, Address offset: 0x008 */ 1233 __IO uint32_t CSR; /*!< PSRAM Control Status register, Address offset: 0x00C */ 1234 __IO uint32_t DRR; /*!< PSRAM Device Refresh/Power-Up register, Address offset: 0x010 */ 1235 1236 __IO u32 RSVD0[4]; /*!< reserved space, 4 Dwords*/ 1237 1238 __IO uint32_t CMD_DPIN_NDGE; /*!< PSRAM Device Cmd/Addr Pin register(Negative Edge), Address offset: 0x024 */ 1239 __IO uint32_t CMD_DPIN; /*!< PSRAM Device Cmd/Addr Pin register(Positive Edge), Address offset: 0x028 */ 1240 __IO uint32_t CR_TDPIN; /*!< PSRAM Tie DPin register, Address offset: 0x02C */ 1241 __IO uint32_t MR_INFO; /*!< PSRAM Mode Latency Information register, Address offset: 0x030 */ 1242 __IO uint32_t MR0; /*!< PSRAM Device CR0 register, Address offset: 0x034 */ 1243 __IO uint32_t MR1; /*!< PSRAM Device CR1 register, Address offset: 0x038 */ 1244 1245 __IO u32 RSVD1[9]; /*!< reserved space, 9 Dwords*/ 1246 1247 __IO uint32_t DPDRI; /*!< PSRAM DPIN Data Index register, Address offset: 0x060 */ 1248 __IO uint32_t DPDR; /*!< PSRAM DPIN Data register, Address offset: 0x064 */ 1249 1250 __IO u32 RSVD2[35]; /*!< reserved space, 35 Dwords*/ 1251 1252 __IO uint32_t PCTL_SVN_ID; /*!< PSRAM_LPC_CTRL Version Numbers register, Address offset: 0x0F4 */ 1253 __IO uint32_t PCTL_IDR; /*!< PSRAM_LPC_CTRL Identification register, Address offset: 0x0F8 */ 1254 1255 __IO u32 RSVD3[193]; /*!< reserved space, 193 Dwords*/ 1256 1257 __IO uint32_t USER0_INDEX; /*!< PSRAM User Extended Index register, Address offset: 0x400 */ 1258 __IO uint32_t USER0_DATA; /*!< PSRAM User Extended Data register, Address offset: 0x404 */ 1259 } PCTL_TypeDef; 1260 /** @} */ 1261 1262 /**************************************************************************//** 1263 * @defgroup AMEBAD_GDMA 1264 * @{ 1265 * @brief AMEBAD_GDMA Register Declaration 1266 *****************************************************************************/ 1267 typedef struct 1268 { 1269 __IO uint32_t SAR; /*!< Channel x Source Address Register, Address offset: 0x0000 */ 1270 uint32_t RSVD0; 1271 __IO uint32_t DAR; /*!< Channel x Destination Address Register, Address offset: 0x0008 */ 1272 uint32_t RSVD1; 1273 __IO uint32_t LLP; /*!< Channel x Linked List Pointer Register, Address offset: 0x0010 */ 1274 uint32_t RSVD2; 1275 __IO uint32_t CTL_LOW; /*!< Channel x Control Register, Address offset: 0x0018 */ 1276 __IO uint32_t CTL_HIGH; /*!< Channel x Control Register, Address offset: 0x001C */ 1277 __IO uint32_t SSTAT; /*!< Channel x Source Status Register, Address offset: 0x0020 */ 1278 uint32_t RSVD4; 1279 __IO uint32_t DSTAT; /*!< Channel x Destination Status Register, Address offset: 0x0028 */ 1280 uint32_t RSVD5; 1281 __IO uint32_t SSTATAR; /*!< Channel x Source Status Address Register, Address offset: 0x0030 */ 1282 uint32_t RSVD6; 1283 __IO uint32_t DSTATAR; /*!< Channel x Destination Status Address Register, Address offset: 0x0038 */ 1284 uint32_t RSVD7; 1285 __IO uint32_t CFG_LOW; /*!< Channel x Configuration Register, Address offset: 0x0040 */ 1286 __IO uint32_t CFG_HIGH; /*!< Channel x Configuration Register, Address offset: 0x0044 */ 1287 __IO uint32_t SGR; /*!< Channel x Source Gather Register, Address offset: 0x0048 */ 1288 uint32_t RSVD9; 1289 __IO uint32_t DSR; /*!< Channel x Source Gather Register, Address offset: 0x0050 */ 1290 uint32_t RSVD10; /*!< Channel x Last Register, Address offset: 0x0054 */ 1291 } GDMA_ChannelTypeDef; 1292 1293 typedef struct 1294 { 1295 GDMA_ChannelTypeDef CH[8]; /*!< GDMA IP have 8 channels, Address offset: 0x00-0x2BC */ 1296 1297 __I uint32_t RAW_TFR; /*!< Raw Status for IntTfr Interrupt, Address offset: 0x02C0 */ 1298 uint32_t RSVD0; 1299 __I uint32_t RAW_BLOCK; /*!< Raw Status for IntBlock Interrupt, Address offset: 0x02C8 */ 1300 uint32_t RSVD1; 1301 __I uint32_t RAW_SRC_TRAN; /*!< Raw Status for IntSrcTran Interrupt, Address offset: 0x02D0 */ 1302 uint32_t RSVD2; 1303 __I uint32_t RAW_DST_TRAN; /*!< Raw Status for IntDstTran Interrupt, Address offset: 0x02D0 */ 1304 uint32_t RSVD3; 1305 __I uint32_t RAW_ERR; /*!< Raw Status for IntErr Interrupt, Address offset: 0x02E0 */ 1306 uint32_t RSVD4; 1307 1308 __I uint32_t STATUS_TFR; /*!< Status for IntTfr Interrupt, Address offset: 0x02E8 */ 1309 uint32_t RSVD5; 1310 __I uint32_t STATUS_BLOCK; /*!< Status for IntBlock Interrupt, Address offset: 0x02F0 */ 1311 uint32_t RSVD6; 1312 __I uint32_t STATUS_SRC_TRAN; /*!< Status for IntSrcTran Interrupt, Address offset: 0x02F8 */ 1313 uint32_t RSVD7; 1314 __I uint32_t STATUS_DST_TRAN; /*!< Status for IntDstTran Interrupt, Address offset: 0x0300 */ 1315 uint32_t RSVD8; 1316 __I uint32_t STATUS_ERR; /*!< Status for IntErr Interrupt, Address offset: 0x0308 */ 1317 uint32_t RSVD9; 1318 1319 __IO uint32_t MASK_TFR; /*!< Mask for IntTfr Interrupt, Address offset: 0x0310 */ 1320 uint32_t RSVD10; 1321 __IO uint32_t MASK_BLOCK; /*!< Mask for IntBlock Interrupt, Address offset: 0x0318 */ 1322 uint32_t RSVD11; 1323 __IO uint32_t MASK_SRC_TRAN; /*!< Mask for IntSrcTran Interrupt, Address offset: 0x0320 */ 1324 uint32_t RSVD12; 1325 __IO uint32_t MASK_DST_TRAN; /*!< Mask for IntDstTran Interrupt, Address offset: 0x0328 */ 1326 uint32_t RSVD13; 1327 __IO uint32_t MASK_ERR; /*!< Mask for IntErr Interrupt, Address offset: 0x0330 */ 1328 uint32_t RSVD14; 1329 1330 __O uint32_t CLEAR_TFR; /*!< Clear for IntTfr Interrupt, Address offset: 0x0338 */ 1331 uint32_t RSVD15; 1332 __O uint32_t CLEAR_BLOCK; /*!< Clear for IntBlock Interrupt, Address offset: 0x0340 */ 1333 uint32_t RSVD16; 1334 __O uint32_t CLEAR_SRC_TRAN; /*!< Clear for IntSrcTran Interrupt, Address offset: 0x0348 */ 1335 uint32_t RSVD17; 1336 __O uint32_t CLEAR_DST_TRAN; /*!< Clear for IntDstTran Interrupt, Address offset: 0x0350 */ 1337 uint32_t RSVD18; 1338 __O uint32_t CLEAR_ERR; /*!< Clear for IntErr Interrupt, Address offset: 0x0358 */ 1339 uint32_t RSVD19; 1340 __O uint32_t StatusInt; /*!< Status for each interrupt type, Address offset: 0x0360 */ 1341 uint32_t RSVD191; 1342 1343 __IO uint32_t ReqSrcReg; /*!< Source Software Transaction Request Register, Address offset: 0x0368 */ 1344 uint32_t RSVD20; 1345 __IO uint32_t ReqDstReg; /*!< Destination Software Transaction Request Register, Address offset: 0x0370 */ 1346 uint32_t RSVD21; 1347 __IO uint32_t SglReqSrcReg; /*!< Single Source Transaction Request Register, Address offset: 0x0378 */ 1348 uint32_t RSVD22; 1349 __IO uint32_t SglReqDstReg; /*!< Single Destination Transaction Request Register, Address offset: 0x0380 */ 1350 uint32_t RSVD23; 1351 __IO uint32_t LstSrcReg; /*!< Last Source Transaction Request Register, Address offset: 0x0388 */ 1352 uint32_t RSVD24; 1353 __IO uint32_t LstDstReg; /*!< Last Destination Transaction Request Register, Address offset: 0x0390 */ 1354 uint32_t RSVD25; 1355 1356 __IO uint32_t DmaCfgReg; /*!< DMA Configuration Register, Address offset: 0x0398 */ 1357 uint32_t RSVD26; 1358 __IO uint32_t ChEnReg; /*!< DMA Channel Enable Register, Address offset: 0x03A0 */ 1359 uint32_t RSVD27; 1360 __I uint32_t DmaIdReg; /*!< DMA ID Register, Address offset: 0x03A8 */ 1361 uint32_t RSVD28; 1362 __IO uint32_t DmaTestReg; /*!< DMA Test Register, Address offset: 0x03B0 */ 1363 uint32_t RSVD29; 1364 } GDMA_TypeDef; 1365 1366 /** @} */ 1367 1368 /**************************************************************************//** 1369 * @defgroup AMEBAD_SDIO_HOST 1370 * @{ 1371 * @brief AMEBAD_SDIO_HOST Register Declaration 1372 *****************************************************************************/ 1373 typedef struct { 1374 __IO uint32_t RSVD1[256]; 1375 __IO uint32_t SRAM_CRL; /*!< SRAM Control Register, Address offset: 0x00000400*/ 1376 __IO uint32_t DMA_CRL1; /*!< DMA Control Register 1, Address offset: 0x00000404*/ 1377 __IO uint32_t DMA_CRL2; /*!< DMA Control Register 2, Address offset: 0x00000408*/ 1378 __IO uint32_t DMA_CRL3; /*!< DMA Control Register 3, Address offset: 0x0000040C*/ 1379 __IO uint32_t SYS_LOW_PWR; /*!< Low Power Control Register, Address offset: 0x00000410*/ 1380 __IO uint32_t RSVD2[4]; 1381 __IO uint32_t SD_ISR; /*!< SD Interrupt Status Register,Address offset: 0x00000424*/ 1382 __IO uint32_t SD_ISREN; /*!< SD Interrupt Enable Register,Address offset: 0x00000428*/ 1383 __IO uint32_t RSVD3[18]; 1384 __IO uint32_t PAD_CTL; /*!< Pad Control Register, Address offset: 0x00000474*/ 1385 __IO uint32_t CKGEN_CTL; /*!< Clock Generation Control Register, Address offset: 0x00000478*/ 1386 __IO uint32_t RSVD4[33]; 1387 __IO uint16_t RSVD5; 1388 __IO uint8_t CARD_DRIVER_SEL; /*!< Card Driving Selection Register,Address offset: 0x00000502*/ 1389 __O uint8_t CARD_STOP; /*!< Stop Transfer Register,Address offset: 0x00000503*/ 1390 __IO uint32_t RSVD6[2]; 1391 __IO uint16_t RSVD7; 1392 __IO uint8_t CARD_SELECT; /*!< Card Type Select Register, Address offset: 0x0000050E*/ 1393 __IO uint8_t DUMMY1; /*!< Dummy Register 1, Address offset: 0x0000050F*/ 1394 __IO uint32_t RSVD8[3]; 1395 __IO uint16_t RSVD9; 1396 __IO uint8_t RSVD10; 1397 __I uint8_t CARD_EXIST; /*!< Card Detection Register, Address offset: 0x0000051F*/ 1398 __IO uint8_t CARD_INT_EN; /*!< Card Interrupt Enable Register,Address offset: 0x00000520*/ 1399 __IO uint8_t CARD_INT_PEND; /*!< Card Interrupt Status Register,Address offset: 0x00000521*/ 1400 __IO uint16_t RSVD11; 1401 __IO uint32_t RSVD12; 1402 __IO uint8_t RSVD13; 1403 __IO uint8_t CARD_CLK_EN_CTL; /*!< Card Clock Enable Control Register,Address offset: 0x00000529*/ 1404 __IO uint16_t RSVD14; 1405 __IO uint32_t RSVD15; 1406 __IO uint8_t CLK_PAD_DRIVE; /*!< Clock Pad Driving Register, Address offset: 0x00000530*/ 1407 __IO uint8_t CMD_PAD_DRIVE; /*!< Command Pad Driving Register ,Address offset: 0x00000531*/ 1408 __IO uint8_t DAT_INT_PEND; /*!< Data Pad Driving Register, Address offset: 0x00000532*/ 1409 __IO uint8_t RSVD16; 1410 __IO uint32_t RSVD17[19]; 1411 __IO uint8_t SD_CONFIG1; /*!< SD Configuration Register 1, Address offset: 0x00000580*/ 1412 __IO uint8_t SD_CONFIG2; /*!< SD Configuration Register 2 ,Address offset: 0x00000581*/ 1413 __IO uint8_t SD_CONFIG3; /*!< SD Configuration Register 3, Address offset: 0x00000582*/ 1414 __I uint8_t SD_STATUS1; /*!< SD Status Register 1 , Address offset: 0x00000583*/ 1415 __IO uint8_t SD_STATUS2; /*!< SD Status Register 2, Address offset: 0x00000584*/ 1416 __IO uint8_t SD_BUS_STATUS; /*!< SD Bus Status Register, Address offset: 0x00000585*/ 1417 __IO uint16_t RSVD18; 1418 __IO uint8_t RSVD19; 1419 __IO uint8_t SD_CMD[6]; /*!< SD Command Register 0-5, Address offset: 0x00000589-0x0000058E*/ 1420 __IO uint8_t SD_BYTE_CNT_L; /*!< Byte Count Register (Low Byte), Address offset: 0x0000058F*/ 1421 __IO uint8_t SD_BYTE_CNT_H; /*!< Byte Count Register (High Byte), Address offset: 0x00000590*/ 1422 __IO uint8_t SD_BLOCK_CNT_L; /*!< Block Count Register (Low Byte), Address offset: 0x00000591*/ 1423 __IO uint8_t SD_BLOCK_CNT_H; /*!< Block Count Register (High Byte), Address offset: 0x00000592*/ 1424 __IO uint8_t SD_TRANSFER; /*!< SD Transfer Control Register, Address offset: 0x00000593*/ 1425 __IO uint8_t RSVD20; 1426 __I uint8_t SD_CMD_STATE; /*!< SD Command State Register, Address offset: 0x00000595*/ 1427 __I uint8_t SD_DATA_STATE; /*!< SD Data State Register, Address offset: 0x00000596*/ 1428 } SDIOH_TypeDef; 1429 /** @} */ 1430 1431 /**************************************************************************//** 1432 * @defgroup AMEBAD_IPC 1433 * @{ 1434 * @brief AMEBAD_IPC Register Declaration 1435 *****************************************************************************/ 1436 typedef struct { 1437 __IO uint32_t IPCx_IER; /*!< Interrupt Enable Register, Address offset: 0x00, Writing a '0' have no effect */ 1438 __IO uint32_t IPCx_IDR; /*!< Interrupt Disable Register, Address offset: 0x04, Writing a '0' have no effect */ 1439 __IO uint32_t IPCx_IRR; /*!< Interrupt Request Register, Address offset: 0x08, Writing a '0' have no effect */ 1440 __IO uint32_t IPCx_ICR; /*!< Interrupt Clear Register, Address offset: 0x0C, Writing a '0' have no effect */ 1441 __IO uint32_t IPCx_CPUID; /*!< CPU ID Register, Address offset: 0x10, RO (Just CM0 Valid) */ 1442 __IO uint32_t IPCx_ISR; /*!< Interrupt Status Register, Address offset: 0x14, RO */ 1443 __IO uint32_t IPC0_SEM; /*!< Hardware Semaphore Register, Address offset: 0x18 (Just CM0 Valid) */ 1444 __IO uint32_t IPCx_IER_R; /*!< Current IER Read register, Address offset: 0x1C, RO */ 1445 __IO uint32_t IPCx_USR[12]; /*!< User defined register, Address offset: 0x0020~0x004C, RW */ 1446 } IPC_TypeDef; 1447 /** @} */ 1448 1449 /**************************************************************************//** 1450 * @defgroup AMEBAD_BACKUP_REG 1451 * @{ 1452 * @brief AMEBAD_BACKUP_REG Register Declaration 1453 * @note 16 Bytes total 1454 *****************************************************************************/ 1455 typedef struct { 1456 __IO uint32_t DWORD[8]; /* 0x3C0 */ 1457 } BACKUP_REG_TypeDef; 1458 /** @} */ 1459 1460 /**************************************************************************//** 1461 * @defgroup AMEBAD_RRAM 1462 * @{ 1463 * @brief AMEBAD_RRAM Declaration 1464 * @ the Max space for RRAM_TypeDef is 0xB0, user can alloc space from RRAM_USER_RSVD 1465 *****************************************************************************/ 1466 typedef struct { 1467 uint8_t RRAM_WIFI_STATUS; /* RETENTION_RAM_SYS_OFFSET 0x80 */ 1468 uint8_t RRAM_WIFI_P_SECURTY; 1469 uint8_t RRAM_WIFI_G_SECURTY; 1470 uint8_t RRAM_RSVD1; 1471 1472 uint32_t RRAM_NET_IP; 1473 uint32_t RRAM_NET_GW; 1474 uint32_t RRAM_NET_GW_MASK; 1475 1476 uint32_t FLASH_ID2; /*offset 0x90*/ 1477 uint32_t FLASH_cur_cmd; 1478 uint32_t FALSH_quad_valid_cmd; 1479 uint32_t FALSH_dual_valid_cmd; 1480 uint32_t FLASH_QuadEn_bit; /*offset 0xA0*/ 1481 uint32_t FLASH_StructInit; 1482 1483 uint8_t FLASH_phase_shift_idx; 1484 uint8_t FLASH_rd_sample_phase_cal; 1485 uint8_t FLASH_class; 1486 uint8_t FLASH_cur_bitmode; 1487 1488 uint8_t FLASH_ClockDiv; 1489 uint8_t FLASH_ReadMode; 1490 uint8_t FLASH_pseudo_prm_en; 1491 uint8_t FLASH_addr_phase_len; 1492 1493 uint8_t FLASH_cmd_wr_status2; /*offset 0xB0*/ 1494 uint8_t FLASH_rd_dummy_cyle0; 1495 uint8_t FLASH_rd_dummy_cyle1; 1496 uint8_t FLASH_rd_dummy_cyle2; 1497 1498 uint8_t RRAM_USER_RSVD[124]; /*usr can alloc from this RSVD space*/ 1499 1500 1501 } RRAM_TypeDef; 1502 /** @} */ 1503 1504 1505 /**************************************************************************//** 1506 * @defgroup AMEBAD_RSIP_REG 1507 * @{ 1508 * @brief AMEBAD_RSIP_REG Register Declaration 1509 * @note Flash MMU & Flash OTF 1510 *****************************************************************************/ 1511 typedef struct { 1512 __IO uint32_t OTF_MASK_ENTRYx_CTRL; /*!< otf mask control */ 1513 __IO uint32_t OTF_MASK_ENTRYx_STRADDR; /*!< otf mask start address */ 1514 } OTF_Mask_TypeDef; 1515 1516 typedef struct { 1517 __IO uint32_t MMU_ENTRYx_CTRL; /*!< flash MMU entry_x control */ 1518 __IO uint32_t MMU_ENTRYx_STRADDR; /*!< flash MMU entry_x virtual address start */ 1519 __IO uint32_t MMU_ENTRYx_ENDADDR; /*!< flash MMU entry_x virtual address end */ 1520 __IO uint32_t MMU_ENTRYx_OFFSET; /*!< flash PAddress = VAddress +/- MMU_ENTRYx_OFFSET */ 1521 } RSIP_MMU_TypeDef; 1522 1523 typedef struct { 1524 __IO uint32_t REG_OTF_DEC_CTRL; /*!< Flash decryption control register, Address offset: 0x000 */ 1525 __IO uint32_t REG_OTF_DEC_IV_EXT[3]; /*!< OTF AES IV[95:0], Address offset: 0x004~0x00C */ 1526 OTF_Mask_TypeDef OTF_MASK[4]; /*!< Flash decryption control register, Address offset: 0x010~0x02C */ 1527 RSIP_MMU_TypeDef FLASH_MMU[8]; /*!< Flash MMU control register, Address offset: 0x030~0x0AF */ 1528 } RSIP_REG_TypeDef; 1529 /** @} */ 1530 /** @} End of group AmebaD_Peripheral_Registers_Structures */ 1531 1532 /**************************************************************************//** 1533 * @defgroup AmebaD_Peripheral_Declaration AmebaD HS/LP Peripheral Declarations 1534 * @{ 1535 *****************************************************************************/ 1536 #define UART0_DEV ((UART_TypeDef *) UART0_REG_BASE) /*KM4 uart0 */ 1537 #define UART1_DEV ((UART_TypeDef *) UART1_REG_BASE) /*KM4 uart1_bt */ 1538 #define UART2_DEV ((UART_TypeDef *) UART2_REG_BASE) /*KM0 log uart */ 1539 #define UART3_DEV ((UART_TypeDef *) UART3_REG_BASE) /*KM0 luart*/ 1540 1541 #define SPI0_DEV ((SPI_TypeDef *) SPI0_REG_BASE) /*KM4 */ 1542 #define SPI1_DEV ((SPI_TypeDef *) SPI1_REG_BASE) /*KM4 */ 1543 #define I2S_DEV ((I2S_TypeDef *) I2S0_REG_BASE) 1544 #define AUDIO_SI_DEV ((AUDIO_SI_TypeDef *) AUDIO_SI_REG_BASE) /*KM4 */ 1545 #define AUDIO_SPORT_DEV ((AUDIO_SPORT_TypeDef *) AUDIO_SPORT_REG_BASE) /*KM4 */ 1546 #define USI0_DEV ((USI_TypeDef *) USI_REG_BASE) /*KM4 */ 1547 #define LCDC ((LCDC_TypeDef *) LCDC_REG_BASE) /*KM4 */ 1548 #define PSRAM_DEV ((PCTL_TypeDef *) PSRAM_REG_BASE) /*KM4 */ 1549 1550 #define SPIC ((SPIC_TypeDef *) SPI_FLASH_CTRL_BASE) 1551 #define ADC ((ADC_TypeDef *) ADC_REG_BASE) 1552 #define COMPARATOR ((CMP_TypeDef *) CMP_REG_BASE) 1553 #define I2C0_DEV ((I2C_TypeDef *) I2C0_REG_BASE) 1554 1555 #define TIM0 ((RTIM_TypeDef *) TIMERM4_REG_BASE) 1556 #define TIM1 ((RTIM_TypeDef *) (TIMERM4_REG_BASE + 0x080)) 1557 #define TIM2 ((RTIM_TypeDef *) (TIMERM4_REG_BASE + 0x100)) 1558 #define TIM3 ((RTIM_TypeDef *) (TIMERM4_REG_BASE + 0x180)) 1559 #define TIM4 ((RTIM_TypeDef *) (TIMERM4_REG_BASE + 0x200)) 1560 #define TIM5 ((RTIM_TypeDef *) (TIMERM4_REG_BASE + 0x280)) 1561 #define TIMM00 ((RTIM_TypeDef *) TIMERM0_REG_BASE) /*KM0 */ 1562 #define TIMM01 ((RTIM_TypeDef *) (TIMERM0_REG_BASE + 0x080)) /*KM0 */ 1563 #define TIMM02 ((RTIM_TypeDef *) (TIMERM0_REG_BASE + 0x100)) /*KM0 */ 1564 #define TIMM03 ((RTIM_TypeDef *) (TIMERM0_REG_BASE + 0x180)) /*KM0 */ 1565 #define TIMM04 ((RTIM_TypeDef *) (TIMERM0_REG_BASE + 0x200)) /*KM0 */ 1566 #define TIMM05 ((RTIM_TypeDef *) (TIMERM0_REG_BASE + 0x280)) /*KM0 */ 1567 1568 #define KEYSCAN_DEV ((KEYSCAN_TypeDef *) KEYSCAN_REG_BASE) /*KM0 */ 1569 #define SGPIO_DEV ((SGPIO_TypeDef *) SGPIO_REG_BASE) /*KM0 */ 1570 #define CAPTOUCH_DEV ((CAPTOUCH_TypeDef *) CTC_REG_BASE) /*KM0 */ 1571 #define IR_DEV ((IR_TypeDef *) IR_REG_BASE) /*KM0 */ 1572 #define QDEC_DEV ((QDEC_TypeDef *) QDEC_REG_BASE) /*KM0 */ 1573 #define RTC_DEV ((RTC_TypeDef *) (RTC_BASE - 0x08000000); /*KM0 */ 1574 #define PINMUX ((PINMUX_TypeDef *) PINMUX_REG_BASE) /*KM0 */ 1575 #define GPIOA_BASE ((GPIO_TypeDef *) GPIO_REG_BASE) /*KM0 */ 1576 #define GPIOB_BASE ((GPIO_TypeDef *) (GPIO_REG_BASE + 0x400)) /*KM0 */ 1577 #define BACKUP_REG ((BACKUP_REG_TypeDef *) BACKUP_REG_BASE) /*KM0 */ 1578 1579 #define KM4_IDAU ((IDAU_TypeDef *) KM4_IDAU_BASE) /*KM4 */ 1580 #define IPCM4_DEV ((IPC_TypeDef *) IPCM4_REG_BASE) /*KM4 */ 1581 #define IPCM0_DEV ((IPC_TypeDef *) IPCM0_REG_BASE) /*KM0 */ 1582 1583 #define GDMA_BASE ((GDMA_TypeDef *) (GDMA0_REG_BASE)) 1584 1585 #define WDG_BASE ((WDG_TypeDef *) (VENDOR_REG_BASE)) 1586 #define RSIP_BASE ((RSIP_REG_TypeDef *) (RSIP_REG_BASE)) 1587 #define SDIOH_BASE ((SDIOH_TypeDef *) (SDIOH_REG_BASE)) 1588 1589 #define RRAM_BASE ((RRAM_TypeDef *) (RETENTION_RAM_BASE + RETENTION_RAM_SYS_OFFSET)) 1590 /** @} End of group AmebaD_Peripheral_Declaration */ 1591 1592 /** @} End of group AmebaD_Outline */ 1593 #endif //_HAL_PLATFORM_ 1594 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 1595