IS_CACHE_LINE_ALIGNED_ADDR (reference) in projects: AliOS-Things-master

Searched refs:IS_CACHE_LINE_ALIGNED_ADDR (Results 1 – 2 of 2) sorted by relevance

/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A D	rtl8721d_cache.h	`65 #define IS_CACHE_LINE_ALIGNED_ADDR(ADDR) ((ADDR & 0x1F) == 0) macro`
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/crypto/
A D	rtl8721dhp_crypto_ram.c	`715 if(!IS_CACHE_LINE_ALIGNED_ADDR(start_addr)) in CRYPTO_Cache_Sync() 736 …if((!IS_CACHE_LINE_ALIGNED_ADDR(end_addr)) && ((end_addr & CACHE_LINE_ADDR_MSK) != (start_addr & C… in CRYPTO_Cache_Sync()`

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