1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __MPU_H__
5 #define __MPU_H__
6 
7 #include "plat_types.h"
8 
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 enum MPU_ID_T {
14     MPU_ID_NULL_POINTER = 0,
15     MPU_ID_1,
16     MPU_ID_2,
17     MPU_ID_3,
18     MPU_ID_4,
19     MPU_ID_5,
20     MPU_ID_6,
21     MPU_ID_7,
22 
23     MPU_ID_QTY,
24 };
25 
26 /*mcu sections */
27 #define MPU_ID_USER_DATA_SECTION    MPU_ID_1
28 #define MPU_ID_FRAM_TEXT1           MPU_ID_2
29 #define MPU_ID_FRAM_TEXT2           MPU_ID_3
30 
31 /*cp sections */
32 #define MPU_ID_CP_FLASHX            MPU_ID_2
33 #define MPU_ID_CP_FLASH             MPU_ID_3
34 #define MPU_ID_CP_FLASH_NC          MPU_ID_4
35 
36 #define MPU_ID_CP_PERIPHERAL        MPU_ID_NULL_POINTER
37 #define MPU_ID_CP_SRAM              MPU_ID_1
38 #define MPU_ID_CP_SRAMX             MPU_ID_5
39 
40 /*both mcu and cp section*/
41 #define MPU_ID_PSRAMUHS             MPU_ID_6
42 #define MPU_ID_PSRAMUHSX            MPU_ID_7
43 
44 enum MPU_ATTR_T {
45     MPU_ATTR_READ_WRITE_EXEC = 0,
46     MPU_ATTR_READ_EXEC,
47     MPU_ATTR_EXEC,
48     MPU_ATTR_READ_WRITE,
49     MPU_ATTR_READ,
50     MPU_ATTR_NO_ACCESS,
51 
52     MPU_ATTR_QTY,
53 };
54 
55 int mpu_open(void);
56 
57 int mpu_close(void);
58 
59 // VALID LENGTH: 32, 64, 128, 256, 512, 1K, 2K, ..., 4G
60 // ADDR must be aligned to len
61 // Note, srd_bits, mpu subregion bits, which can be divided to 8 sub regions
62 // per region, if don't need, always set the arguments to 0;
63 int mpu_set(enum MPU_ID_T id, uint32_t addr, uint32_t len, int srd_bits,
64                                                     enum MPU_ATTR_T attr);
65 
66 int mpu_clear(enum MPU_ID_T id);
67 
68 int mpu_null_check_enable(void);
69 
70 int mpu_fast_ram_protect(void);
71 
72 void mpu_open_for_psramuhs();
73 
74 int mpu_set_armv8_psramuhs(enum MPU_ID_T id, uint32_t addr, uint32_t len, enum MPU_ATTR_T attr);
75 
76 #ifdef __cplusplus
77 }
78 #endif
79 
80 #endif
81 
82