1 /**
2   ******************************************************************************
3   * @file    rtl8711b_clk.h
4   * @author
5   * @version V1.0.0
6   * @date    2016-05-17
7   * @brief   This file provides firmware functions to manage the following
8   *          functionalities of clock control:
9   *           - NCO32K clock
10   *           - NCO8M clock
11   *           - CPU clock
12   *           - XTAL clock get
13   *           - OSC32K clock
14   *           - EXT32K clock
15   ******************************************************************************
16   * @attention
17   *
18   * This module is a confidential and proprietary property of RealTek and
19   * possession or use of this module requires written permission of RealTek.
20   *
21   * Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
22   ******************************************************************************
23   */
24 
25 #ifndef _RTL8721D_CLK_H_
26 #define _RTL8721D_CLK_H_
27 
28 /** @addtogroup AmebaD_Platform
29   * @{
30   */
31 
32 /** @defgroup CLOCK
33   * @brief CLOCK driver modules
34   * @{
35   */
36 
37 /** @addtogroup CLOCK
38   * @verbatim
39   *****************************************************************************************
40   * NCO32K
41   *****************************************************************************************
42   *	-RTC clock in
43   *	-TIM0-TIM3 clock in
44   *	-WIFI 32K clock in
45   *****************************************************************************************
46   * OSC32K OSC8M
47   *****************************************************************************************
48   *	-OSC32K is used to calibration OSC8M
49   *	-OSC8M is used for LP UART when SOC suspend and close XTAL
50   *****************************************************************************************
51   *****************************************************************************************
52   * NCO8M
53   *****************************************************************************************
54   *	-used for LP UART when SOC active
55   *	-Clock in is XTAL (40MHz)
56   *	-Clock out is 8MHz
57   *
58   *****************************************************************************************
59   * HS CPU clock
60   *****************************************************************************************
61   *	-CLK_KM4_200M: 200MHz
62   *	-CLK_KM4_100M: 100MHz
63   *	-CLK_KM4_50M: 50MHz
64   *	-CLK_KM4_25M: 25MHz
65   *	-CLK_KM4_XTAL: XTAL
66   *
67   *****************************************************************************************
68   * XTAL clock
69   *****************************************************************************************
70   *	-Get XTAL clock from EFUSE setting:
71   *	-40000000
72   *	-25000000
73   *	-13000000
74   *	-19200000
75   *	-20000000
76   *	-26000000
77   *	-38400000
78   *	-17664000
79   *	-16000000
80   *	-14318000
81   *	-12000000
82   *	-52000000
83   *	-48000000
84   *	-26000000
85   *	-27000000
86   *	-24000000
87 
88   *****************************************************************************************
89   * EXT32K
90   *****************************************************************************************
91   *	-External 32K: 32K clock from external 32k source
92   *	-Internal 32K: 32K clock from internal 32K source: NCO32K
93   *
94   *****************************************************************************************
95   * @endverbatim
96   */
97 
98 /* Exported constants --------------------------------------------------------*/
99 
100 /** @defgroup CLK_Exported_Constants CLK Exported Constants
101   * @{
102   */
103 
104 /** @defgroup SDM32K_Cal_Type_definitions
105   * @{
106   */
107 #define SDM32K_ONE_CAL			0
108 #define SDM32K_AUTO_CAL		1
109 #define SDM32K_ALWAYS_CAL		2
110 /**
111   * @}
112   */
113 
114 /** @defgroup LP_CPU_CLK_definitions
115   * @{
116   */
117 #define CLK_KM0_XTAL		0 /* if XTAL is 26MHz, we can use it */
118 #define CLK_KM0_XTALDIV2	1 /* if XTAL is 40MHz, we should use it */
119 #define CLK_KM0_ANA_4M		2 /* if XTAL OFF, default config */
120 /**
121   * @}
122   */
123 
124 /** @defgroup HS_CPU_CLK_definitions
125   * @{
126   */
127 #define CLK_KM4_200M		0
128 #define CLK_KM4_100M		1
129 #define CLK_KM4_50M			2
130 #define CLK_KM4_25M			3
131 #define CLK_KM4_XTAL		4
132 /**
133   * @}
134   */
135 
136 /** @defgroup PLL_SEL_definitions
137   * @{
138   */
139 #define PLL_I2S		0
140 #define PLL_PCM		1
141 
142 /** @defgroup PLL_ClkTune_definitions
143   * @{
144   */
145 #define PLL_AUTO		0
146 #define PLL_FASTER		1
147 #define PLL_SLOWER		2
148 
149 /**
150   * @}
151   */
152 
153 /** @defgroup OSC2M_Cal_definitions
154   * @{
155   */
156 #define OSC2M_CAL_CYC_16	0
157 #define OSC2M_CAL_CYC_32	1
158 #define OSC2M_CAL_CYC_64	2
159 #define OSC2M_CAL_CYC_128	3
160 /**
161   * @}
162   */
163 
164 /**
165   * @}
166   */
167 
168 /* Exported functions --------------------------------------------------------*/
169 /** @defgroup SDM32K_CLK_Exported_Functions SDM32K_CLK Exported Functions
170   * @{
171   */
172 _LONG_CALL_ void SDM32K_Enable(u32 AutoCalibration);
173 _LONG_CALL_ void SDM32K_RTCCalEnable(u32 RTCCalibration);
174 /**
175   * @}
176   */
177 
178 /** @defgroup EXT32K_CLK_Exported_Functions EXT32K_CLK Exported Functions
179   * @{
180   */
181 _LONG_CALL_ void EXT32K_Cmd(u32 NewStatus);
182 /**
183   * @}
184   */
185 
186 /** @defgroup CPU_CLK_Exported_Functions CPU_CLK Exported Functions
187   * @{
188   */
189 _LONG_CALL_ u32 CPU_ClkGet(u8 Is_FPGA);
190 _LONG_CALL_ void CPU_ClkSet(u8  CpuType);
191 /**
192   * @}
193   */
194 
195 /** @defgroup XTAL_CLK_Exported_Functions XTAL_CLK Exported Functions
196   * @{
197   */
198 _LONG_CALL_ u32 XTAL_ClkGet(void);
199 /**
200   * @}
201   */
202 
203 /** @defgroup NCO2M_CLK_Exported_Functions NCO2M_CLK Exported Functions
204   * @{
205   */
206 _LONG_CALL_ void NCO2M_Init(u32 clk_out_Hz);
207 _LONG_CALL_ void NCO2M_Cmd(u32 NewState);
208 /**
209   * @}
210   */
211 
212 /** @defgroup PLL_Exported_Functions PLL Exported Functions
213   * @{
214   */
215 _LONG_CALL_ void PLL_I2S_Set(u32 new_state);
216 _LONG_CALL_ void PLL_PCM_Set(u32 new_state);
217 _LONG_CALL_ void PLL2_Set(u32 BitMask, u32 NewState);
218 _LONG_CALL_ void PLL3_Set(u32 BitMask, u32 NewState);
219 /**
220   * @}
221   */
222 
223 /* Registers Definitions --------------------------------------------------------*/
224 /**************************************************************************//**
225  * @defgroup CLK_Register_Definitions CLK Register Definitions
226  * @{
227  *****************************************************************************/
228 
229 /**************************************************************************//**
230  * @defgroup REG_SYS_SYSPLL_CTRL2
231  * @{
232  *****************************************************************************/
233 #define BIT_SYS_SYSPLL_CK_ADC_EN		(0x00000001 << 25) /*!< Set ADC PLL EN */
234 /** @} */
235 
236 /** @} */
237 
238 /**
239   * @}
240   */
241 
242 /**
243   * @}
244   */
245 
246 /**
247   * @}
248   */
249 
250 /* Other definations --------------------------------------------------------*/
251 u32 OSC2M_Calibration(u32 cal_osc_cycles, u32 ppm_limit);
252 u32 OSC131K_Calibration(u32 ppm_limit);
253 void OSC4M_Init(void);
254 
255 #endif //_RTL8721D_CLK_H_
256 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
257