1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef PSRAM_REG_H
5 #define PSRAM_REG_H
6 
7 #include "plat_types.h"
8 
9 /* ip register */
10 /* 0x0 */
11 #define PSRIP_CMD_ADDR_REG_OFFSET 0x0
12 #define PSRIP_CMD_ADDR_ADDR_SHIFT (8)
13 #define PSRIP_CMD_ADDR_ADDR_MASK ((0xfffffff)<<PSRIP_CMD_ADDR_ADDR_SHIFT)
14 #define PSRIP_CMD_ADDR_CMD_SHIFT (0)
15 #define PSRIP_CMD_ADDR_CMD_MASK ((0xf)<<PSRIP_CMD_ADDR_CMD_SHIFT)
16 
17 /* 0x4 */
18 #define PSRIP_ACCSIZE_REG_OFFSET 0x4
19 #define PSRIP_ACCSIZE_SIZE_SHIFT (0)
20 #define PSRIP_ACCSIZE_SIZE_MASK ((0xf)<<PSRIP_ACCSIZE_SIZE_SHIFT)
21 
22 /* 0x8 */
23 #define PSRIP_TX_DATA_REG_OFFSET 0x8
24 #define PSRIP_TX_DATA_DATA_SHIFT (0)
25 #define PSRIP_TX_DATA_DATA_MASK ((0xff)<<PSRIP_TX_DATA_DATA_SHIFT)
26 
27 /* 0xc */
28 #define PSRIP_STAT_REG_OFFSET 0x0c
29 #define PSRIP_STAT_RX_COUNT_SHIFT (4)
30 #define PSRIP_STAT_RX_COUNT_MASK ((0x1f)<<PSRIP_STAT_RX_COUNT_SHIFT)
31 #define PSRIP_STAT_RX_EMPTY_SHIFT (3)
32 #define PSRIP_STAT_RX_EMPTY_MASK ((0x1)<<PSRIP_STAT_RX_EMPTY_SHIFT)
33 #define PSRIP_STAT_TX_FULL_SHIFT (2)
34 #define PSRIP_STAT_TX_FULL_MASK ((0x1)<<PSRIP_STAT_TX_FULL_SHIFT)
35 #define PSRIP_STAT_TX_EMPTY_SHIFT (1)
36 #define PSRIP_STAT_TX_EMPTY_MASK ((0x1)<<PSRIP_STAT_TX_EMPTY_SHIFT)
37 #define PSRIP_STAT_BUSY_SHIFT (0)
38 #define PSRIP_STAT_BUSY_MASK ((0x1)<<PSRIP_STAT_BUSY_SHIFT)
39 
40 /* 0x10 */
41 #define PSRIP_RX_DATA_REG_OFFSET 0x10
42 #define PSRIP_RX_DATA_DATA_SHIFT (0)
43 #define PSRIP_RX_DATA_DATA_MASK ((0xff)<<PSRIP_RX_DATA_DATA_SHIFT)
44 
45 /* 0x14 */
46 #define PSRIP_DUMMY_REG_OFFSET 0x14
47 #define PSRIP_DUMMY_WAIT_SHIFT (0)
48 #define PSRIP_DUMMY_WAIT_MASK ((0xf)<<PSRIP_DUMMY_WAIT_SHIFT)
49 
50 /* 0x18 */
51 #define PSRIP_FIFOCLR_REG_OFFSET 0x18
52 #define PSRIP_FIFOCLR_CLR_TX_SHIFT (1)
53 #define PSRIP_FIFOCLR_CLR_TX_MASK ((0x1)<<PSRIP_FIFOCLR_CLR_TX_SHIFT)
54 #define PSRIP_FIFOCLR_CLR_RX_SHIFT (0)
55 #define PSRIP_FIFOCLR_CLR_RX_MASK ((0x1)<<PSRIP_FIFOCLR_CLR_RX_SHIFT)
56 
57 /* 0x1c */
58 #define PSRIP_LSPCTRL_REG_OFFSET 0x1c
59 #define PSRIP_LSPCTRL_LPCSHIWAIT_SHIFT (16)
60 #define PSRIP_LSPCTRL_LPCSHIWAIT_MASK ((0xffff)<<PSRIP_LSPCTRL_LPCSHIWAIT_SHIFT)
61 #define PSRIP_LSPCTRL_LPCSLOWWAIT_SHIFT (12)
62 #define PSRIP_LSPCTRL_LPCSLOWWAIT_MASK ((0xf)<<PSRIP_LSPCTRL_LPCSLOWWAIT_SHIFT)
63 #define PSRIP_LSPCTRL_RES_SHIFT (8)
64 #define PSRIP_LSPCTRL_RES_MASK ((0xf)<<PSRIP_LSPCTRL_RES_SHIFT)
65 #define PSRIP_LSPCTRL_CABCLK90PRE_SHIFT (0)
66 #define PSRIP_LSPCTRL_CABCLK90PRE_MASK ((0xff)<<PSRIP_LSPCTRL_CABCLK90PRE_SHIFT)
67 
68 /* removed */
69 /* 0x20 */
70 #define PSRIP_PHYOCTR_REG_OFFSET 0x20
71 #define PSRIP_PHYOCTR_PU_SHIFT (0)
72 #define PSRIP_PHYOCTR_PU_MASK ((0x1)<<PSRIP_PHYOCTR_PU_SHIFT)
73 
74 /* 0x24 */
75 #define PSRIP_MODECALIBR_REG_OFFSET 0x24
76 #define PSRIP_MODECALIBR_NHS_CLK_PREDIV_SHIFT (16)
77 #define PSRIP_MODECALIBR_NHS_CLK_PREDIV_MASK ((0xff)<<PSRIP_MODECALIBR_NHS_CLK_PREDIV_SHIFT)
78 #define PSRIP_MODECALIBR_RES_SHIFT (11)
79 #define PSRIP_MODECALIBR_RES_MASK ((0x1f)<<PSRIP_MODECALIBR_RES_SHIFT)
80 #define PSRIP_MODECALIBR_DQS_RD_SEL_SHIFT (8)
81 #define PSRIP_MODECALIBR_DQS_RD_SEL_MASK ((0x7)<<PSRIP_MODECALIBR_DQS_RD_SEL_SHIFT)
82 #define PSRIP_MODECALIBR_DQS_WR_SEL_SHIFT (4)
83 #define PSRIP_MODECALIBR_DQS_WR_SEL_MASK ((0x7)<<PSRIP_MODECALIBR_DQS_WR_SEL_SHIFT)
84 #define PSRIP_MODECALIBR_CALIBST_SHIFT (3)
85 #define PSRIP_MODECALIBR_CALIBST_MASK ((0x1)<<PSRIP_MODECALIBR_CALIBST_SHIFT)
86 #define PSRIP_MODECALIBR_ENABLE_CALIB_SHIFT (1)
87 #define PSRIP_MODECALIBR_ENABLE_CALIB_MASK ((0x1)<<PSRIP_MODECALIBR_ENABLE_CALIB_SHIFT)
88 #define PSRIP_MODECALIBR_TRIGGER_SHIFT (0)
89 #define PSRIP_MODECALIBR_TRIGGER_MASK ((0x1)<<PSRIP_MODECALIBR_TRIGGER_SHIFT)
90 
91 /* 0x28 */
92 #define PSRIP_SPWKUPCTRL1_REG_OFFSET 0x28
93 #define PSRIP_SPWKUPCTRL1_SLPWKUPSTAT_SHIFT (16)
94 #define PSRIP_SPWKUPCTRL1_SLPWKUPSTAT_MASK ((0x3)<<PSRIP_SPWKUPCTRL1_SLPWKUPSTAT_SHIFT)
95 #define PSRIP_SPWKUPCTRL1_ONPROCESS_SHIFT (1)
96 #define PSRIP_SPWKUPCTRL1_ONPROCESS_MASK ((0x1)<<PSRIP_SPWKUPCTRL1_ONPROCESS_SHIFT)
97 #define PSRIP_SPWKUPCTRL1_SLP_WKUP_SHIFT (0)
98 #define PSRIP_SPWKUPCTRL1_SLP_WKUP_MASK ((0x1)<<PSRIP_SPWKUPCTRL1_SLP_WKUP_SHIFT)
99 
100 /* 0x2C */
101 #define PSRIP_SPWKUPCTRL2_REG_OFFSET 0x2C
102 #define PSRIP_SPWKUPCTRL2_SLPWKUPSTAT_SHIFT (16)
103 #define PSRIP_SPWKUPCTRL2_SLPWKUPSTAT_MASK ((0x3)<<PSRIP_SPWKUPCTRL2_SLPWKUPSTAT_SHIFT)
104 #define PSRIP_SPWKUPCTRL2_HIGH_DENSITY_EN_SHIFT (1)
105 #define PSRIP_SPWKUPCTRL2_HIGH_DENSITY_EN_MASK ((0x1)<<PSRIP_SPWKUPCTRL2_HIGH_DENSITY_EN_SHIFT)
106 #define PSRIP_SPWKUPCTRL2_WRAP_MODE_ENABLE_SHIFT (3)
107 #define PSRIP_SPWKUPCTRL2_WRAP_MODE_ENABLE_MASK ((0x1)<<PSRIP_SPWKUPCTRL2_WRAP_MODE_ENABLE_SHIFT)
108 #define PSRIP_SPWKUPCTRL2_WRAPTYPE_MODE_SHIFT (2)
109 #define PSRIP_SPWKUPCTRL2_1KWRAPTYPE_MODE_MASK ((0x1)<<PSRIP_SPWKUPCTRL2_WRAPTYPE_MODE_SHIFT)
110 #define PSRIP_SPWKUPCTRL2_32BYTEWRAPTYPE_MODE_MASK ((0x1)<<PSRIP_SPWKUPCTRL2_WRAPTYPE_MODE_SHIFT)
111 #define PSRIP_SPWKUPCTRL2_HS_MODE_SHIFT (0)
112 #define PSRIP_SPWKUPCTRL2_HS_MODE_MASK ((0x1)<<PSRIP_SPWKUPCTRL2_HS_MODE_SHIFT)
113 
114 #endif /* PSRAM_REG_H */
115 
116