1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __REG_PWM_H__
5 #define __REG_PWM_H__
6 
7 #include "plat_types.h"
8 
9 // PWM Registers
10 struct PWM_T
11 {
12     __I  uint32_t ID;               // 0x000
13     __IO uint32_t EN;               // 0x004
14     __IO uint32_t INV;              // 0x008
15     __IO uint32_t PHASE01;          // 0x00C
16     __IO uint32_t PHASE23;          // 0x010
17     __IO uint32_t LOAD01;           // 0x014
18     __IO uint32_t LOAD23;           // 0x018
19     __IO uint32_t TOGGLE01;         // 0x01C
20     __IO uint32_t TOGGLE23;         // 0x020
21     __IO uint32_t PHASEMOD;         // 0x024
22     __IO uint32_t ST1_23;           // 0x028
23     __IO uint32_t TWINKLE23;        // 0x02C
24 };
25 
26 #define PWM_EN_0                    (1 << 0)
27 #define PWM_EN_1                    (1 << 1)
28 #define PWM_EN_2                    (1 << 2)
29 #define PWM_EN_3                    (1 << 3)
30 
31 #define PWM_INV_0                   (1 << 0)
32 #define PWM_INV_1                   (1 << 1)
33 #define PWM_INV_2                   (1 << 2)
34 #define PWM_INV_3                   (1 << 3)
35 
36 #define PWM_PHASE01_0(n)            (((n) & 0xFFFF) << 0)
37 #define PWM_PHASE01_0_MASK          (0xFFFF << 0)
38 #define PWM_PHASE01_0_SHIFT         (0)
39 #define PWM_PHASE01_1(n)            (((n) & 0xFFFF) << 16)
40 #define PWM_PHASE01_1_MASK          (0xFFFF << 16)
41 #define PWM_PHASE01_1_SHIFT         (16)
42 
43 #define PWM_PHASE23_2(n)            (((n) & 0xFFFF) << 0)
44 #define PWM_PHASE23_2_MASK          (0xFFFF << 0)
45 #define PWM_PHASE23_2_SHIFT         (0)
46 #define PWM_PHASE23_3(n)            (((n) & 0xFFFF) << 16)
47 #define PWM_PHASE23_3_MASK          (0xFFFF << 16)
48 #define PWM_PHASE23_3_SHIFT         (16)
49 
50 #define PWM_LOAD01_0(n)             (((n) & 0xFFFF) << 0)
51 #define PWM_LOAD01_0_MASK           (0xFFFF << 0)
52 #define PWM_LOAD01_0_SHIFT          (0)
53 #define PWM_LOAD01_1(n)             (((n) & 0xFFFF) << 16)
54 #define PWM_LOAD01_1_MASK           (0xFFFF << 16)
55 #define PWM_LOAD01_1_SHIFT          (16)
56 
57 #define PWM_LOAD23_2(n)             (((n) & 0xFFFF) << 0)
58 #define PWM_LOAD23_2_MASK           (0xFFFF << 0)
59 #define PWM_LOAD23_2_SHIFT          (0)
60 #define PWM_LOAD23_3(n)             (((n) & 0xFFFF) << 16)
61 #define PWM_LOAD23_3_MASK           (0xFFFF << 16)
62 #define PWM_LOAD23_3_SHIFT          (16)
63 
64 #define PWM_TOGGLE01_0(n)           (((n) & 0xFFFF) << 0)
65 #define PWM_TOGGLE01_0_MASK         (0xFFFF << 0)
66 #define PWM_TOGGLE01_0_SHIFT        (0)
67 #define PWM_TOGGLE01_1(n)           (((n) & 0xFFFF) << 16)
68 #define PWM_TOGGLE01_1_MASK         (0xFFFF << 16)
69 #define PWM_TOGGLE01_1_SHIFT        (16)
70 
71 #define PWM_TOGGLE23_2(n)           (((n) & 0xFFFF) << 0)
72 #define PWM_TOGGLE23_2_MASK         (0xFFFF << 0)
73 #define PWM_TOGGLE23_2_SHIFT        (0)
74 #define PWM_TOGGLE23_3(n)           (((n) & 0xFFFF) << 16)
75 #define PWM_TOGGLE23_3_MASK         (0xFFFF << 16)
76 #define PWM_TOGGLE23_3_SHIFT        (16)
77 
78 #define PWM_PHASEMOD_0              (1 << 0)
79 #define PWM_PHASEMOD_1              (1 << 1)
80 #define PWM_PHASEMOD_2              (1 << 2)
81 #define PWM_PHASEMOD_3              (1 << 3)
82 
83 #endif
84 
85