1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef __REG_NORFLASHIP_V2_H__ 5 #define __REG_NORFLASHIP_V2_H__ 6 7 #include "plat_types.h" 8 9 struct NORFLASH_CTRL_T { 10 __IO uint32_t REG_000; 11 __IO uint32_t REG_004; 12 union TXDATA_REG_T { 13 __IO uint32_t TXWORD; 14 __IO uint16_t TXHALFWORD; 15 __IO uint8_t TXBYTE; 16 } REG_008; 17 __IO uint32_t REG_00C; 18 __IO uint32_t REG_010; 19 __IO uint32_t REG_014; 20 __IO uint32_t REG_018; 21 __IO uint32_t REG_01C; 22 __IO uint32_t REG_020; 23 __IO uint32_t REG_024; 24 __IO uint32_t REG_028; 25 __IO uint32_t REG_02C; 26 __IO uint32_t REG_030; 27 __IO uint32_t REG_034; 28 #if !defined(CHIP_BEST2300) 29 __IO uint32_t REG_038; 30 __IO uint32_t RESERVED_03C; 31 __IO uint32_t REG_040; 32 __IO uint32_t RESERVED_044[3]; 33 __IO uint32_t REG_050; 34 __IO uint32_t REG_054; 35 __IO uint32_t REG_058; 36 __IO uint32_t REG_05C; 37 __IO uint32_t REG_060; 38 __IO uint32_t REG_064; 39 __IO uint32_t REG_068; 40 __IO uint32_t REG_06C; 41 #if !defined(CHIP_BEST1400) 42 __IO uint32_t REG_070; 43 __IO uint32_t REG_074; 44 __IO uint32_t REG_078; 45 __IO uint32_t REG_07C; 46 __IO uint32_t REG_080; 47 __IO uint32_t REG_084; 48 __IO uint32_t REG_088; 49 __IO uint32_t REG_08C; 50 __IO uint32_t REG_090; 51 __IO uint32_t REG_094; 52 __IO uint32_t REG_098; 53 __IO uint32_t REG_09C; 54 __IO uint32_t REG_0A0; 55 __IO uint32_t RESERVED_0A4[3]; 56 __IO uint32_t REG_0B0; 57 #if (CHIP_FLASH_CTRL_VER >= 3) 58 __IO uint32_t RESERVED_0B4[0x13]; 59 __IO uint32_t REG_100; 60 __IO uint32_t REG_104; 61 __IO uint32_t REG_108; 62 __IO uint32_t REG_10C; 63 __IO uint32_t REG_110; 64 __IO uint32_t REG_114; 65 __IO uint32_t REG_118; 66 __IO uint32_t REG_11C; 67 __IO uint32_t REG_120; 68 __IO uint32_t REG_124; 69 __IO uint32_t REG_128; 70 __IO uint32_t REG_12C; 71 __IO uint32_t REG_130; 72 __IO uint32_t REG_134; 73 __IO uint32_t REG_138; 74 __IO uint32_t REG_13C; 75 __IO uint32_t REG_140; 76 __IO uint32_t REG_144; 77 __IO uint32_t REG_148; 78 __IO uint32_t REG_14C; 79 __IO uint32_t REG_150; 80 #endif 81 #endif 82 #endif 83 }; 84 85 // REG_000 86 #define REG_000_ADDR_SHIFT 8 87 #define REG_000_ADDR_MASK (0xFFFFFF << REG_000_ADDR_SHIFT) 88 #define REG_000_ADDR(n) BITFIELD_VAL(REG_000_ADDR, n) 89 #define REG_000_CMD_SHIFT 0 90 #define REG_000_CMD_MASK (0xFF << REG_000_CMD_SHIFT) 91 #define REG_000_CMD(n) BITFIELD_VAL(REG_000_CMD, n) 92 93 #define REG_000_NEW_CMD_RX_LEN_SHIFT 13 94 #define REG_000_NEW_CMD_RX_LEN_MASK (0x3FFF << REG_000_NEW_CMD_RX_LEN_SHIFT) 95 #define REG_000_NEW_CMD_RX_LEN(n) BITFIELD_VAL(REG_000_NEW_CMD_RX_LEN, n) 96 #define REG_000_NEW_CMD_RX_LINE_SHIFT 11 97 #define REG_000_NEW_CMD_RX_LINE_MASK (0x3 << REG_000_NEW_CMD_RX_LINE_SHIFT) 98 #define REG_000_NEW_CMD_RX_LINE(n) BITFIELD_VAL(REG_000_NEW_CMD_RX_LINE, n) 99 #define REG_000_NEW_CMD_TX_LINE_SHIFT 9 100 #define REG_000_NEW_CMD_TX_LINE_MASK (0x3 << REG_000_NEW_CMD_TX_LINE_SHIFT) 101 #define REG_000_NEW_CMD_TX_LINE(n) BITFIELD_VAL(REG_000_NEW_CMD_TX_LINE, n) 102 #define REG_000_NEW_CMD_RX_EN (1 << 8) 103 104 #define NEW_CMD_LINE_4X 2 105 #define NEW_CMD_LINE_2X 1 106 #define NEW_CMD_LINE_1X 0 107 108 // REG_004 109 #define REG_004_RES26_SHIFT 26 110 #define REG_004_RES26_MASK (0x3F << REG_004_RES26_SHIFT) 111 #define REG_004_RES26(n) BITFIELD_VAL(REG_004_RES26, n) 112 #define REG_004_CONTINUOUS_MODE (1 << 25) 113 #define REG_004_BLOCK_SIZE_SHIFT 12 114 #define REG_004_BLOCK_SIZE_MASK (0x1FFF << REG_004_BLOCK_SIZE_SHIFT) 115 #define REG_004_BLOCK_SIZE(n) BITFIELD_VAL(REG_004_BLOCK_SIZE, n) 116 #define REG_004_MODEBIT_SHIFT 4 117 #define REG_004_MODEBIT_MASK (0xFF << REG_004_MODEBIT_SHIFT) 118 #define REG_004_MODEBIT(n) BITFIELD_VAL(REG_004_MODEBIT, n) 119 #define REG_004_RES1_SHIFT 1 120 #define REG_004_RES1_MASK (0x7 << REG_004_RES1_SHIFT) 121 #define REG_004_RES1(n) BITFIELD_VAL(REG_004_RES1, n) 122 #define REG_004_NEW_CMD_EN (1 << 0) 123 124 // REG_008 125 #define REG_008_TXDATA_SHIFT 0 126 #define REG_008_TXDATA_MASK (0xFFFFFFFF << REG_008_TXDATA_SHIFT) 127 #define REG_008_TXDATA(n) BITFIELD_VAL(REG_008_TXDATA, n) 128 129 // REG_00C 130 #define REG_00C_RES_SHIFT 13 131 #define REG_00C_RES_MASK (0x7FFFF << REG_00C_RES_SHIFT) 132 #define REG_00C_RES(n) BITFIELD_VAL(REG_00C_RES, n) 133 #define REG_00C_TXFIFO_EMPCNT_SHIFT 8 134 #define REG_00C_TXFIFO_EMPCNT_MASK (0x1F << REG_00C_TXFIFO_EMPCNT_SHIFT) 135 #define REG_00C_TXFIFO_EMPCNT(n) BITFIELD_VAL(REG_00C_TXFIFO_EMPCNT, n) 136 #define REG_00C_RXFIFO_COUNT_SHIFT 4 137 #define REG_00C_RXFIFO_COUNT_MASK (0xF << REG_00C_RXFIFO_COUNT_SHIFT) 138 #define REG_00C_RXFIFO_COUNT(n) BITFIELD_VAL(REG_00C_RXFIFO_COUNT, n) 139 #define REG_00C_RXFIFO_EMPTY (1 << 3) 140 #define REG_00C_TXFIFO_FULL (1 << 2) 141 #define REG_00C_TXFIFO_EMPTY (1 << 1) 142 #define REG_00C_BUSY (1 << 0) 143 144 // REG_010 145 #define REG_010_RXDATA_SHIFT 0 146 #define REG_010_RXDATA_MASK (0xFFFFFFFF << REG_010_RXDATA_SHIFT) 147 #define REG_010_RXDATA(n) BITFIELD_VAL(REG_010_RXDATA, n) 148 149 // REG_014 150 #define REG_014_RES29_SHIFT 29 151 #define REG_014_RES29_MASK (0x7 << REG_014_RES29_SHIFT) 152 #define REG_014_RES29(n) BITFIELD_VAL(REG_014_RES29, n) 153 #define REG_014_EXTRA_SHSL_SHIFT 25 154 #define REG_014_EXTRA_SHSL_MASK (0xF << REG_014_EXTRA_SHSL_SHIFT) 155 #define REG_014_EXTRA_SHSL(n) BITFIELD_VAL(REG_014_EXTRA_SHSL, n) 156 #define REG_014_EXTRA_SHSL_EN (1 << 24) 157 #define REG_014_CLKDIV_SHIFT 16 158 #define REG_014_CLKDIV_MASK (0xFF << REG_014_CLKDIV_SHIFT) 159 #define REG_014_CLKDIV(n) BITFIELD_VAL(REG_014_CLKDIV, n) 160 #define REG_014_SAMPLESEL_SHIFT 12 161 #define REG_014_SAMPLESEL_MASK (0xF << REG_014_SAMPLESEL_SHIFT) 162 #define REG_014_SAMPLESEL(n) BITFIELD_VAL(REG_014_SAMPLESEL, n) 163 // Since 2300p 164 #define EXTRA_TCHSH_O_SHIFT 8 165 #define EXTRA_TCHSH_O_MASK (0xF << EXTRA_TCHSH_O_SHIFT) 166 #define EXTRA_TCHSH_O(n) BITFIELD_VAL(EXTRA_TCHSH_O, n) 167 #define EXTRA_TCHSH_EN_O (1 << 7) 168 // End of since 2300p 169 #define REG_014_CMDQUAD (1 << 6) 170 #define REG_014_RAM_DUALMODE (1 << 5) 171 #define REG_014_RAM_QUADMODE (1 << 4) 172 #define REG_014_FOUR_BYTE_ADDR_EN (1 << 3) 173 #define REG_014_RES2 (1 << 2) 174 #define REG_014_HOLDPIN (1 << 1) 175 #define REG_014_WPROPIN (1 << 0) 176 177 // REG_018 178 #define REG_018_RES_SHIFT 2 179 #define REG_018_RES_MASK (0x3FFFFFFF << REG_018_RES_SHIFT) 180 #define REG_018_RES(n) BITFIELD_VAL(REG_018_RES, n) 181 #define REG_018_TXFIFOCLR (1 << 1) 182 #define REG_018_RXFIFOCLR (1 << 0) 183 184 // REG_01C 185 #define REG_01C_RES18_SHIFT 18 186 #define REG_01C_RES18_MASK (0x3FFF << REG_01C_RES18_SHIFT) 187 #define REG_01C_RES18(n) BITFIELD_VAL(REG_01C_RES18, n) 188 #define REG_01C_DMA_RX_SIZE_SHIFT 16 189 #define REG_01C_DMA_RX_SIZE_MASK (0x3 << REG_01C_DMA_RX_SIZE_SHIFT) 190 #define REG_01C_DMA_RX_SIZE(n) BITFIELD_VAL(REG_01C_DMA_RX_SIZE, n) 191 #define REG_01C_TX_THRESHOLD_SHIFT 8 192 #define REG_01C_TX_THRESHOLD_MASK (0x1F << REG_01C_TX_THRESHOLD_SHIFT) 193 #define REG_01C_TX_THRESHOLD(n) BITFIELD_VAL(REG_01C_TX_THRESHOLD, n) 194 #define REG_01C_RX_THRESHOLD_SHIFT 4 195 #define REG_01C_RX_THRESHOLD_MASK (0xF << REG_01C_RX_THRESHOLD_SHIFT) 196 #define REG_01C_RX_THRESHOLD(n) BITFIELD_VAL(REG_01C_RX_THRESHOLD, n) 197 #define REG_01C_RES3 (1 << 3) 198 #define REG_01C_DMACTRL_RX_EN (1 << 2) 199 #define REG_01C_DMACTRL_TX_EN (1 << 1) 200 #define REG_01C_NAND_SEL (1 << 0) 201 202 // REG_020 203 #define REG_020_DUALCMD_SHIFT 24 204 #define REG_020_DUALCMD_MASK (0xFF << REG_020_DUALCMD_SHIFT) 205 #define REG_020_DUALCMD(n) BITFIELD_VAL(REG_020_DUALCMD, n) 206 #define REG_020_READCMD_SHIFT 16 207 #define REG_020_READCMD_MASK (0xFF << REG_020_READCMD_SHIFT) 208 #define REG_020_READCMD(n) BITFIELD_VAL(REG_020_READCMD, n) 209 #define REG_020_FREADCMD_SHIFT 8 210 #define REG_020_FREADCMD_MASK (0xFF << REG_020_FREADCMD_SHIFT) 211 #define REG_020_FREADCMD(n) BITFIELD_VAL(REG_020_FREADCMD, n) 212 #define REG_020_QUADCMD_SHIFT 0 213 #define REG_020_QUADCMD_MASK (0xFF << REG_020_QUADCMD_SHIFT) 214 #define REG_020_QUADCMD(n) BITFIELD_VAL(REG_020_QUADCMD, n) 215 216 // REG_024 217 #define REG_024_CMD_SEQ1_SHIFT 0 218 #define REG_024_CMD_SEQ1_MASK (0xFFFFFFFF << REG_024_CMD_SEQ1_SHIFT) 219 #define REG_024_CMD_SEQ1(n) BITFIELD_VAL(REG_024_CMD_SEQ1, n) 220 221 // REG_028 222 #define REG_028_CMD_SEQ_EN (1 << 4) 223 #define REG_028_CMD_SEQ2_SHIFT 0 224 #define REG_028_CMD_SEQ2_MASK (0xF << REG_028_CMD_SEQ2_SHIFT) 225 #define REG_028_CMD_SEQ2(n) BITFIELD_VAL(REG_028_CMD_SEQ2, n) 226 227 // REG_02C 228 #define REG_02C_RES_SHIFT 1 229 #define REG_02C_RES_MASK (0x7FFFFFFF << REG_02C_RES_SHIFT) 230 #define REG_02C_RES(n) BITFIELD_VAL(REG_02C_RES, n) 231 #define REG_02C_FETCH_EN (1 << 0) 232 233 // REG_030 234 #define REG_030_RES_SHIFT 2 235 #define REG_030_RES_MASK (0x3FFFFFFF << REG_030_RES_SHIFT) 236 #define REG_030_RES(n) BITFIELD_VAL(REG_030_RES, n) 237 #define REG_030_ADDR_25_24_SHIFT 0 238 #define REG_030_ADDR_25_24_MASK (0x3 << REG_030_ADDR_25_24_SHIFT) 239 #define REG_030_ADDR_25_24(n) BITFIELD_VAL(REG_030_ADDR_25_24, n) 240 241 // REG_034 242 #define REG_034_RES_SHIFT 22 243 #define REG_034_RES_MASK (0x3FF << REG_034_RES_SHIFT) 244 #define REG_034_RES(n) BITFIELD_VAL(REG_034_RES, n) 245 #define REG_034_SPI_IOEN_SHIFT 18 246 #define REG_034_SPI_IOEN_MASK (0xF << REG_034_SPI_IOEN_SHIFT) 247 #define REG_034_SPI_IOEN(n) BITFIELD_VAL(REG_034_SPI_IOEN, n) 248 #define REG_034_SPI_IODRV_SHIFT 16 249 #define REG_034_SPI_IODRV_MASK (0x3 << REG_034_SPI_IODRV_SHIFT) 250 #define REG_034_SPI_IODRV(n) BITFIELD_VAL(REG_034_SPI_IODRV, n) 251 #define REG_034_SPI_IORES_SHIFT 8 252 #define REG_034_SPI_IORES_MASK (0xFF << REG_034_SPI_IORES_SHIFT) 253 #define REG_034_SPI_IORES(n) BITFIELD_VAL(REG_034_SPI_IORES, n) 254 #define REG_034_SPI_RDEN_SHIFT 4 255 #define REG_034_SPI_RDEN_MASK (0xF << REG_034_SPI_RDEN_SHIFT) 256 #define REG_034_SPI_RDEN(n) BITFIELD_VAL(REG_034_SPI_RDEN, n) 257 #define REG_034_SPI_RUEN_SHIFT 0 258 #define REG_034_SPI_RUEN_MASK (0xF << REG_034_SPI_RUEN_SHIFT) 259 #define REG_034_SPI_RUEN(n) BITFIELD_VAL(REG_034_SPI_RUEN, n) 260 261 // REG_038 262 #define REG_038_MAN_WRAP_BITS_SHIFT 13 263 #define REG_038_MAN_WRAP_BITS_MASK (0x3 << REG_038_MAN_WRAP_BITS_SHIFT) 264 #define REG_038_MAN_WRAP_BITS(n) BITFIELD_VAL(REG_038_MAN_WRAP_BITS, n) 265 #define REG_038_MAN_WRAP_ENABLE_SHIFT 12 266 #define REG_038_MAN_WRAP_ENABLE_MASK (0x1 << REG_038_MAN_WRAP_ENABLE_SHIFT) 267 #define REG_038_MAN_WRAP_ENABLE (REG_038_MAN_WRAP_ENABLE_MASK) 268 #define REG_038_AUTO_WRAP_CMD_SHIFT 4 269 #define REG_038_AUTO_WRAP_CMD_MASK (0xFF << REG_038_AUTO_WRAP_CMD_SHIFT) 270 #define REG_038_AUTO_WRAP_CMD(n) BITFIELD_VAL(REG_038_AUTO_WRAP_CMD, n) 271 #define REG_038_WRAP_MODE_SEL_SHIFT 0 272 #define REG_038_WRAP_MODE_SEL_MASK (0x1 << REG_038_WRAP_MODE_SEL_SHIFT) 273 #define REG_038_WRAP_MODE_SEL (REG_038_WRAP_MODE_SEL_MASK) 274 275 #if (CHIP_FLASH_CTRL_VER >= 3) 276 // REG_40 277 #define REG_40_RES_31_6_SHIFT 6 278 #define REG_40_RES_31_6_MASK (0x3FFFFFF << REG_40_RES_31_6_SHIFT) 279 #define REG_40_RES_31_6(n) BITFIELD_VAL(REG_40_RES_31_6, n) 280 #define REG_40_SPH (1 << 5) 281 #define REG_40_RES_4 (1 << 4) 282 #define REG_40_DQS_MODE (1 << 3) 283 #define REG_40_DTR_MODE (1 << 2) 284 #define REG_40_OPI_MODE (1 << 1) 285 #define REG_40_QPI_MODE (1 << 0) 286 #endif 287 288 // REG_058 289 #define REG_058_IDX_SHIFT 0 290 #define REG_058_IDX_MASK (0x7 << REG_058_IDX_SHIFT) 291 #define REG_058_IDX(n) BITFIELD_VAL(REG_058_IDX, n) 292 293 // REG_060 294 #define REG_060_ADDR_BGN_SHIFT 0 295 #define REG_060_ADDR_BGN_MASK (0xFFFFFFFF << REG_060_ADDR_BGN_SHIFT) 296 #define REG_060_ADDR_BGN(n) BITFIELD_VAL(REG_060_ADDR_BGN, n) 297 298 // REG_064 299 #define REG_064_ADDR_END_SHIFT 0 300 #define REG_064_ADDR_END_MASK (0xFFFFFFFF << REG_064_ADDR_END_SHIFT) 301 #define REG_064_ADDR_END(n) BITFIELD_VAL(REG_064_ADDR_END, n) 302 303 // REG_06C 304 #define REG_06C_DEC_ENABLE_SHIFT 0 305 #define REG_06C_DEC_ENABLE_MASK (0x1 << REG_06C_DEC_ENABLE_SHIFT) 306 #define REG_06C_DEC_ENABLE (REG_06C_DEC_ENABLE_MASK) 307 308 // REG_0A0 309 #ifdef CHIP_BEST2300P 310 #define REG_0A0_LEN_WIDTH3_SHIFT 12 311 #define REG_0A0_LEN_WIDTH3_MASK (0xF << REG_0A0_LEN_WIDTH3_SHIFT) 312 #define REG_0A0_LEN_WIDTH3(n) BITFIELD_VAL(REG_0A0_LEN_WIDTH3, n) 313 #define REG_0A0_LEN_WIDTH2_SHIFT 8 314 #define REG_0A0_LEN_WIDTH2_MASK (0xF << REG_0A0_LEN_WIDTH2_SHIFT) 315 #define REG_0A0_LEN_WIDTH2(n) BITFIELD_VAL(REG_0A0_LEN_WIDTH2, n) 316 #define REG_0A0_LEN_WIDTH1_SHIFT 4 317 #define REG_0A0_LEN_WIDTH1_MASK (0xF << REG_0A0_LEN_WIDTH1_SHIFT) 318 #define REG_0A0_LEN_WIDTH1(n) BITFIELD_VAL(REG_0A0_LEN_WIDTH1, n) 319 #define REG_0A0_LEN_WIDTH0_SHIFT 0 320 #define REG_0A0_LEN_WIDTH0_MASK (0xF << REG_0A0_LEN_WIDTH0_SHIFT) 321 #define REG_0A0_LEN_WIDTH0(n) BITFIELD_VAL(REG_0A0_LEN_WIDTH0, n) 322 #endif 323 324 // REG_0B0 325 #define REG_0B0_ADDR3_REMAP_EN (1 << 4) 326 #define REG_0B0_ADDR2_REMAP_EN (1 << 3) 327 #define REG_0B0_ADDR1_REMAP_EN (1 << 2) 328 #define REG_0B0_ADDR0_REMAP_EN (1 << 1) 329 #define REG_0B0_GLB_REMAP_EN (1 << 0) 330 // End of since 2300p 331 332 #if (CHIP_FLASH_CTRL_VER >= 3) 333 // REG_100 334 #define REG_100_DUMMY_READ_SHIFT 0 335 #define REG_100_DUMMY_READ_MASK (0x1F << REG_100_DUMMY_READ_SHIFT) 336 #define REG_100_DUMMY_READ(n) BITFIELD_VAL(REG_100_DUMMY_READ, n) 337 338 // REG_104 339 #define REG_104_DUMMY_DIOR_SHIFT 0 340 #define REG_104_DUMMY_DIOR_MASK (0x1F << REG_104_DUMMY_DIOR_SHIFT) 341 #define REG_104_DUMMY_DIOR(n) BITFIELD_VAL(REG_104_DUMMY_DIOR, n) 342 343 // REG_108 344 #define REG_108_DUMMY_QIOR_SHIFT 0 345 #define REG_108_DUMMY_QIOR_MASK (0x1F << REG_108_DUMMY_QIOR_SHIFT) 346 #define REG_108_DUMMY_QIOR(n) BITFIELD_VAL(REG_108_DUMMY_QIOR, n) 347 348 // REG_10C 349 #define REG_10C_DUMMY_FREAD_SHIFT 0 350 #define REG_10C_DUMMY_FREAD_MASK (0x1F << REG_10C_DUMMY_FREAD_SHIFT) 351 #define REG_10C_DUMMY_FREAD(n) BITFIELD_VAL(REG_10C_DUMMY_FREAD, n) 352 353 // REG_110 354 #define REG_110_DUMMY_DOR_SHIFT 0 355 #define REG_110_DUMMY_DOR_MASK (0x1F << REG_110_DUMMY_DOR_SHIFT) 356 #define REG_110_DUMMY_DOR(n) BITFIELD_VAL(REG_110_DUMMY_DOR, n) 357 358 // REG_114 359 #define REG_114_DUMMY_QOR_SHIFT 0 360 #define REG_114_DUMMY_QOR_MASK (0x1F << REG_114_DUMMY_QOR_SHIFT) 361 #define REG_114_DUMMY_QOR(n) BITFIELD_VAL(REG_114_DUMMY_QOR, n) 362 363 // REG_118 364 #define REG_118_DUMMY_QIOWR_SHIFT 0 365 #define REG_118_DUMMY_QIOWR_MASK (0x1F << REG_118_DUMMY_QIOWR_SHIFT) 366 #define REG_118_DUMMY_QIOWR(n) BITFIELD_VAL(REG_118_DUMMY_QIOWR, n) 367 368 // REG_11C 369 #define REG_11C_DUMMY_BRWR_SHIFT 0 370 #define REG_11C_DUMMY_BRWR_MASK (0x1F << REG_11C_DUMMY_BRWR_SHIFT) 371 #define REG_11C_DUMMY_BRWR(n) BITFIELD_VAL(REG_11C_DUMMY_BRWR, n) 372 373 // REG_120 374 #define REG_120_DUMMY_BFRD_SHIFT 0 375 #define REG_120_DUMMY_BFRD_MASK (0x1F << REG_120_DUMMY_BFRD_SHIFT) 376 #define REG_120_DUMMY_BFRD(n) BITFIELD_VAL(REG_120_DUMMY_BFRD, n) 377 378 // REG_124 379 #define REG_124_DUMMY_DTRFRD_SHIFT 0 380 #define REG_124_DUMMY_DTRFRD_MASK (0x1F << REG_124_DUMMY_DTRFRD_SHIFT) 381 #define REG_124_DUMMY_DTRFRD(n) BITFIELD_VAL(REG_124_DUMMY_DTRFRD, n) 382 383 // REG_128 384 #define REG_128_DUMMY_DTR2RD_SHIFT 0 385 #define REG_128_DUMMY_DTR2RD_MASK (0x1F << REG_128_DUMMY_DTR2RD_SHIFT) 386 #define REG_128_DUMMY_DTR2RD(n) BITFIELD_VAL(REG_128_DUMMY_DTR2RD, n) 387 388 // REG_12C 389 #define REG_12C_DUMMY_DTR4RD_SHIFT 0 390 #define REG_12C_DUMMY_DTR4RD_MASK (0x1F << REG_12C_DUMMY_DTR4RD_SHIFT) 391 #define REG_12C_DUMMY_DTR4RD(n) BITFIELD_VAL(REG_12C_DUMMY_DTR4RD, n) 392 393 // REG_130 394 #define REG_130_DUMMY_DTRRWR_SHIFT 0 395 #define REG_130_DUMMY_DTRRWR_MASK (0x1F << REG_130_DUMMY_DTRRWR_SHIFT) 396 #define REG_130_DUMMY_DTRRWR(n) BITFIELD_VAL(REG_130_DUMMY_DTRRWR, n) 397 398 // REG_134 399 #define REG_134_DUMMY_OCTFRD_SHIFT 0 400 #define REG_134_DUMMY_OCTFRD_MASK (0x1F << REG_134_DUMMY_OCTFRD_SHIFT) 401 #define REG_134_DUMMY_OCTFRD(n) BITFIELD_VAL(REG_134_DUMMY_OCTFRD, n) 402 403 // REG_138 404 #define REG_138_DUMMY_OCTIORD_SHIFT 0 405 #define REG_138_DUMMY_OCTIORD_MASK (0x1F << REG_138_DUMMY_OCTIORD_SHIFT) 406 #define REG_138_DUMMY_OCTIORD(n) BITFIELD_VAL(REG_138_DUMMY_OCTIORD, n) 407 408 // REG_13C 409 #define REG_13C_DUMMY_4BDTROCTRD_SHIFT 0 410 #define REG_13C_DUMMY_4BDTROCTRD_MASK (0x1F << REG_13C_DUMMY_4BDTROCTRD_SHIFT) 411 #define REG_13C_DUMMY_4BDTROCTRD(n) BITFIELD_VAL(REG_13C_DUMMY_4BDTROCTRD, n) 412 413 // REG_150 414 #define REG_150_DUMMY_OTHERS_SHIFT 0 415 #define REG_150_DUMMY_OTHERS_MASK (0x1F << REG_150_DUMMY_OTHERS_SHIFT) 416 #define REG_150_DUMMY_OTHERS(n) BITFIELD_VAL(REG_150_DUMMY_OTHERS, n) 417 #endif 418 419 #endif 420 421