1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __NORFLASH_CFG_H__
5 #define __NORFLASH_CFG_H__
6 
7 #ifdef __cplusplus
8 extern "C" {
9 #endif
10 
11 #include "plat_types.h"
12 
13 #define STATUS_S10_LB_BIT_SHIFT             2
14 #define STATUS_S10_LB_BIT_MASK              (1 << STATUS_S10_LB_BIT_SHIFT)
15 
16 #define STATUS_S11_LB1_BIT_SHIFT            3
17 #define STATUS_S11_LB1_BIT_MASK             (1 << STATUS_S11_LB1_BIT_SHIFT)
18 
19 enum SEC_REG_BASE_T {
20     SEC_REG_BASE_0X1000,
21     SEC_REG_BASE_0X0000,
22 };
23 
24 enum SEC_REG_SIZE_T {
25     SEC_REG_SIZE_1024,
26     SEC_REG_SIZE_512,
27     SEC_REG_SIZE_256,
28 };
29 
30 enum SEC_REG_OFFSET_T {
31     SEC_REG_OFFSET_0X1000,
32     SEC_REG_OFFSET_0X0100,
33 };
34 
35 enum SEC_REG_CNT_T {
36     SEC_REG_CNT_3,
37     SEC_REG_CNT_4,
38 };
39 
40 enum SEC_REG_PP_T {
41     SEC_REG_PP_256,
42     SEC_REG_PP_1024,
43 };
44 
45 enum SEC_REG_LB_T {
46     SEC_REG_LB_S11_S13,
47     SEC_REG_LB_S10,
48 };
49 
50 struct norflash_cfg_struct_t {
51     uint8_t neg_phase:1;
52     uint8_t pos_neg:1;
53     uint8_t cmdquad:1;
54     uint8_t samdly:3;
55 
56     uint8_t div; /* least 2 */
57 
58     uint8_t dualmode:1;
59     uint8_t holdpin:1;
60     uint8_t wprpin:1;
61     uint8_t quadmode:1;
62     uint8_t mod_clk:4;
63 
64     uint8_t spiruen:3;
65     uint8_t spirden:3;
66 
67     uint8_t dualiocmd;
68     uint8_t rdcmd;
69     uint8_t frdcmd;
70     uint8_t qrdcmd; /* quad io cmd */
71 };
72 
73 #ifdef __cplusplus
74 }
75 #endif
76 
77 #endif
78 
79