Searched refs:SP_CLK_DIV (Results 1 – 2 of 2) sorted by relevance

/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/
A D	rtl8721dhp_audio.c	68 SPORTx->SP_CLK_DIV = 0x271 | (0x10 << 16) | SP_CLK_MI_NI_UPDATE; in AUDIO_SP_Init()
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A D	hal_platform.h	944 __IO uint32_t SP_CLK_DIV; /*!< SPORT clock divide register, Address offset: 0x1C */ member

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