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Searched refs:SYS_CLK_CTRL1 (Results 1 – 2 of 2) sorted by relevance

/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Drtl8721dlp_rcc.h61 #define SYS_CLK_CTRL1 0x01 //0x214 macro
71 #define APBPeriph_GPIO_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_GPIO0_CKE)
72 #define APBPeriph_QDEC0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_QDEC0_CKE)
73 #define APBPeriph_SGPIO_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_SPGIO0_CKE)
74 #define APBPeriph_I2C0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_I2C0_CKE)
75 #define APBPeriph_ADC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_ADC_CKE)
76 #define APBPeriph_UART1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_UART1_CKE)
77 #define APBPeriph_LOGUART_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_UART0_CKE)
78 #define APBPeriph_GTIMER_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_TIMER0_CKE)
79 #define APBPeriph_IPC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_IPC_CKE)
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A Drtl8721dhp_rcc.h61 #define SYS_CLK_CTRL1 0x03 //0x210 macro
68 #define APBPeriph_AUDIOC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HSYS_AC_CK)
69 #define APBPeriph_VENDOR_REG_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_VNDR_CKE)
70 #define APBPeriph_USI_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_USI_CKE)
71 #define APBPeriph_IRDA_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IRDA_CKE)
72 #define APBPeriph_IPC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IPC_CKE)
73 #define APBPeriph_GTIMER_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_TIMER0_CKE)
74 #define APBPeriph_SPI1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI1_CKE)
75 #define APBPeriph_SPI0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI0_CKE)
76 #define APBPeriph_UART1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_UART1_CKE)
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