1 /*
2  * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3  */
4 
5 
6 /**************************************************************************//**
7  * @file     soc.h
8  * @brief    CSI Core Peripheral Access Layer Header File for
9  *           CSKYSOC Device Series
10  * @version  V1.0
11  * @date     02. June 2017
12  ******************************************************************************/
13 
14 #ifndef _SOC_H_
15 #define _SOC_H_
16 
17 #include <stdint.h>
18 #include <csi_core.h>
19 #include <sys_freq.h>
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 #ifndef IHS_VALUE
26 #define  IHS_VALUE    (20000000)
27 #endif
28 
29 #ifndef EHS_VALUE
30 #define  EHS_VALUE    (20000000)
31 #endif
32 
33 /* -------------------------  Interrupt Number Definition  ------------------------ */
34 
35 typedef enum IRQn {
36     /* ----------------------  SmartL Specific Interrupt Numbers  --------------------- */
37     Supervisor_Software_IRQn        =   1,
38     Machine_Software_IRQn           =   3,
39     Supervisor_Timer_IRQn           =   5,
40     CORET_IRQn                      =   7,
41     Supervisor_External_IRQn        =   9,
42     Machine_External_IRQn           =   11,
43     UART_IRQn                       =   32+0,     /* uart Interrupt */
44     TIM0_IRQn                       =   32+2,     /* timer0 Interrupt */
45     TIM1_IRQn                       =   32+3,     /* timer1 Interrupt */
46     TIM2_IRQn                       =   32+4,     /* timer1 Interrupt */
47     TIM3_IRQn                       =   32+5,     /* timer1 Interrupt */
48     GPIO0_IRQn                      =   32+6,     /* gpio0 Interrupt */
49     GPIO1_IRQn                      =   32+7,     /* gpio1 Interrupt */
50     GPIO2_IRQn                      =   32+8,     /* gpio2 Interrupt */
51     GPIO3_IRQn                      =   32+9,     /* gpio3 Interrupt */
52     GPIO4_IRQn                      =   32+10,     /* gpio4 Interrupt */
53     GPIO5_IRQn                      =   32+11,     /* gpio5 Interrupt */
54     GPIO6_IRQn                      =   32+12,     /* gpio6 Interrupt */
55     GPIO7_IRQn                      =   32+13,     /* gpio7 Interrupt */
56     STIM0_IRQn                      =   32+14,     /* stimer0 Interrupt */
57     STIM1_IRQn                      =   32+15,     /* stimer0 Interrupt */
58     STIM2_IRQn                      =   32+16,     /* stimer0 Interrupt */
59     STIM3_IRQn                      =   32+17,     /* stimer0 Interrupt */
60     PAD_IRQn                        =   32+18,     /* pad Interrupt */
61 }
62 IRQn_Type;
63 
64 /* ================================================================================ */
65 /* ================       Device Specific Peripheral Section       ================ */
66 /* ================================================================================ */
67 
68 #define CONFIG_TIMER_NUM    4
69 #define CONFIG_USART_NUM    1
70 #define CONFIG_GPIO_NUM     8
71 #define CONFIG_GPIO_PIN_NUM 8
72 
73 /* ================================================================================ */
74 /* ================              Peripheral memory map             ================ */
75 /* ================================================================================ */
76 /* --------------------------  CPU FPGA memory map  ------------------------------- */
77 #define CSKY_SRAM_BASE              (0x20000000UL)
78 
79 #define CSKY_UART_BASE              (0x10015000UL)
80 #define CSKY_PMU_BASE               (0x10016000UL)
81 #define CSKY_TIMER0_BASE            (0x10011000UL)
82 #define CSKY_TIMER1_BASE            (0x10011014UL)
83 #define CSKY_TIMER2_BASE            (0x10011028UL)
84 #define CSKY_TIMER3_BASE            (0x1001103cUL)
85 #define CSKY_TIMER_CONTROL_BASE     (0x100110a0UL)
86 #define CSKY_CLK_GEN_BASE           (0x10017000UL)
87 #define CSKY_STIMER0_BASE           (0x10018000UL)
88 #define CSKY_STIMER1_BASE           (0x10018014UL)
89 #define CSKY_STIMER2_BASE           (0x10018028UL)
90 #define CSKY_STIMER3_BASE           (0x1001803cUL)
91 #define CSKY_STIMER_CONTROL_BASE    (0x100110a0UL)
92 
93 #define CSKY_GPIOA_BASE             (0x10019000UL)
94 #define CSKY_GPIOA_CONTROL_BASE     (0x10019030UL)
95 #define CSKY_SMPU_BASE              (0x1001a000UL)
96 
97 /* ================================================================================ */
98 /* ================             Peripheral declaration             ================ */
99 /* ================================================================================ */
100 #define CSKY_UART                  ((   CSKY_UART_TypeDef *)    CSKY_UART_BASE)
101 
102 #ifdef __cplusplus
103 }
104 #endif
105 
106 #endif  /* _SOC_H_ */
107