1 /** 2 ****************************************************************************** 3 * @file rtl8721d_usi_ssi.h 4 * @author 5 * @version V1.0.0 6 * @date 2017-11-27 7 * @brief This file contains all the functions prototypes for the SPI firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8721D_USI_SSI_H_ 20 #define _RTL8721D_USI_SSI_H_ 21 22 #include "rtl8721d_usi.h" 23 24 /** @addtogroup AmebaD_Periph_Driver 25 * @{ 26 */ 27 28 /** @defgroup USI-SPI 29 * @brief USI-SPI driver modules 30 * @{ 31 */ 32 33 /** @addtogroup USI-SPI 34 * @verbatim 35 ***************************************************************************************** 36 * Introduction 37 ***************************************************************************************** 38 * USI-SPI: 39 * - Support Motorola SPI interface 40 * - Role: Master or Slave 41 * - Base Address: USI0_DEV 42 * - Bus Clk: 50MHz 43 * - BaudRate: less than or equal to 25M 44 * - Transfer mode: Tx,Rx,TRx when configured as Master; TRx when configured as Slave 45 * - Data Frame Size: 4-16 bits supported 46 * - IRQ Number: USI_IRQ 47 * - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_TX 48 * - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_RX 49 * 50 ***************************************************************************************** 51 * How to use Normal USI SPI 52 ***************************************************************************************** 53 * To use the SPI in normal mode, the following steps are mandatory: 54 * 55 * 1. Enable peripheral clock using the following functions: 56 * -RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE); 57 * 58 * 2. Configure the SPIx pinmux: 59 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master; 60 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave; 61 * 62 * 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize, 63 * Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using 64 * USI_SSI_StructInit() and change some parameters if needed 65 * 66 * 4. Init Hardware use step3 parameters: 67 * USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct) 68 * 69 * 5. Enable the SPI: 70 * USI_SSI_Cmd() 71 * 72 * 6. When using poll: 73 * -Using USI_SSI_Writeable() function to make sure that the transmit FIFO is not full, 74 * then using USI_SSI_WriteData() function to send data 75 * 76 * -Using USI_SSI_Readable() function to make sure that the receive FIFO is not empty, 77 * then using USI_SSI_ReadData() function to receive data 78 * 79 * 7. Enable the NVIC and the corresponding interrupt using following function if you need 80 * to use interrupt mode. 81 * -USI_SSI_INTConfig(): SPI IRQ Mask set 82 * -InterruptRegister(): register the SPI irq handler 83 * -InterruptEn(): Enable the NVIC interrupt and set irq priority 84 * 85 * 86 * @note in SPI_Exported_Functions group, these functions below are about Interrupts 87 * and flags management: 88 * -USI_SSI_GetIsr() 89 * -USI_SSI_GetRawIsr() 90 * -USI_SSI_INTConfig() 91 * -USI_SSI_SetRxFifoLevel() 92 * -USI_SSI_SetTxFifoLevel() 93 * -USI_SSI_SetIsrClean() 94 * 95 * 96 ***************************************************************************************** 97 * How to use USI SPI in DMA mode 98 ***************************************************************************************** 99 * To use the USI SPI in DMA mode, the following steps are mandatory: 100 * 101 * 1. Enable peripheral clock using the following functions: 102 * -RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE); 103 * 104 * 2. Configure the SPIx pinmux: 105 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master; 106 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave; 107 * 108 * 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize, 109 * Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using 110 * USI_SSI_StructInit() and change some parameters if needed 111 * 112 * 4. Init Hardware use step3 parameters: 113 * USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct) 114 * 115 * 5. Enable the SPI: 116 * USI_SSI_Cmd() 117 * 118 * 6. GDMA related configurations(DMA burst size/source address/destination address/block size etc). 119 * 120 * 7. Active the SPI DMA TX/RX using USI_SSI_SetDmaEnable() function. 121 * 122 * @note in SPI_Exported_Functions group, these functions below are about DMA: 123 * -USI_SSI_SetDmaEnable() 124 * -USI_SSI_SetDmaLevel() 125 * 126 ***************************************************************************************** 127 * @endverbatim 128 */ 129 130 /* Exported Types --------------------------------------------------------*/ 131 /** @defgroup USI_SPI_Exported_Types USI-SPI Exported Types 132 * @{ 133 */ 134 135 /** 136 * @brief USI-SPI Init structure definition 137 */ 138 typedef struct 139 { 140 u32 USI_SPI_DmaRxDataLevel; /*!< Specifies the DMA receive data level. 141 The dma_rx_req is generated when the number of valid data entries in the 142 receive FIFO is equal to or above this field value+1,and rxdma_en =1. 143 @note For AmebaD, the value range of this parameter should be 0 to 63,because 144 the depth of Rx FIFO is 64. */ 145 146 u32 USI_SPI_DmaTxDataLevel; /*!< Specifies the DMA transmit data level. 147 The dma_tx_req is generated when the number of valid data entries in the 148 transmit FIFO is equal to or below this field value,and txdma_en =1. 149 @note For AmebaD, the value range of this parameter should be 0 to 63,because 150 the depth of Rx FIFO is 64. */ 151 152 u32 USI_SPI_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level. 153 This Parameter controls the level of entries(or above) at which the receive FIFO controller 154 triggers an interrupt.When the number of receive FIFO entries is greater than or equal to this 155 value +1,the receive FIFO full interrupt is triggered. 156 @note For AmebaD, the value range of this parameter should be 0 to 63,because the depth 157 of Rx FIFO is 64. */ 158 159 u32 USI_SPI_TxThresholdLevel; /*!< Specifies the transmit FIFO threshold level. 160 This Parameter controls the level of entries (or below) at which the transmit FIFO controller 161 triggers an interrupt.When the number of transmit FIFO entries is less than or equal to this 162 value,the transmit FIFO empty interrupt is triggered. 163 @note For AmebaD, the value range of this parameter should be 0 to 63,because of the depth 164 of Rx FIFO is 64. */ 165 166 u32 USI_SPI_ClockDivider; /*!< Specifies the SPI Baud Rate. 167 The value of sclk_out equals to ssi_clk devides the value of this parameter 168 @note The LSB for this field is always set to 0 and is unaffected by a write operation,which ensures 169 an even value is held. */ 170 171 u32 USI_SPI_DataFrameNumber; /*!< Specifies the number of data frames master wants to receive. 172 When TMOD=10, SPI uses this value to set the number of data frames to 173 be continuous received. 174 @note The value of this parameter should be set to the number of data frames that to be received 175 minus one.And this parameter is used only when the device is master. */ 176 177 u32 USI_SPI_DataFrameSize; /*!< Selects the data frame length . 178 This parameter can be a value of @ref USI_SPI_Data_Frame_Size_definitions. 179 @note Need to right-justify transmit data before writting into the transmit FIFO 180 The transmit logic ignores the upper unused bits when transmitting the data. */ 181 182 u32 USI_SPI_InterruptMask; /*!< Specifies which interrupt to enable. 183 Each bit in this parameter corresponds to a specific interrupt.*/ 184 185 u32 USI_SPI_Role; /*!< Specifies the role of SPI device. 186 This parameter can be a value of @ref USI_SPI_ROLE_definitions. . */ 187 188 u32 USI_SPI_SclkPhase; /*!< Specifies the serial clock phase. 189 When USI_SPI_SclkPhase = 0, data are captured on the first edge of the serial clock. 190 When USI_SPI_SclkPhase = 1, the serial clock starts toggling one cycle after the slave select line is activated, 191 and data are captured on the second edge of the serial clock. 192 This parameter can be a value of @ref USI_SPI_SCPH_definitions. */ 193 194 u32 USI_SPI_SclkPolarity; /*!< Specifies the serial clock polarity. 195 When USI_SPI_SclkPolarity = 0, the serial clock remains low when idle. 196 When USI_SPI_SclkPolarity = 1, the serial clock remains high when idle. 197 This parameter can be a value of @ref USI_SPI_SCPOL_definitions. */ 198 199 u32 USI_SPI_TransferMode; /*!< Selects the mode of transfer for serial communication. 200 This parameter can be a value of @ref USI_SPI_TMOD_definitions. 201 @note This transfer mode is only valid when the DW_apb_ssi is configured as a master device.*/ 202 203 u32 USI_SPI_RxSampleDelay; /*!< Specifies the sample delay time of receive data input signal.The unit is spi_mst_clk. 204 @note This configuration is only valid when the DW_apb_ssi is configured as a master device. 205 For AmebaD, the value range of this parameter should be 0 to 0xFF */ 206 207 u32 USI_SPI_SSTogglePhase; /*!< Specifies whether CS needs to toggle between transmissions when USI_SPI_SclkPhase = 0. 208 This parameter can be a value of @ref USI_SPI_SS_Toggle_Phase_definitions. 209 @note This configuration is only valid when the DW_apb_ssi is configured as a master device. */ 210 }USI_SSI_InitTypeDef; 211 212 /** 213 * @} 214 */ 215 216 /* Exported constants --------------------------------------------------------*/ 217 218 /** @defgroup USI_SPI_Exported_Constants USI-SPI Exported Constants 219 * @{ 220 */ 221 222 /** @defgroup USI_SPI_TMOD_definitions 223 * @{ 224 */ 225 #define USI_SPI_TMOD_TR (0) 226 #define USI_SPI_TMOD_TO (1) 227 #define USI_SPI_TMOD_RO (2) 228 /** 229 * @} 230 */ 231 232 /** @defgroup USI_SPI_SCPOL_definitions 233 * @{ 234 */ 235 #define USI_SPI_SCPOL_INACTIVE_IS_LOW (0) 236 #define USI_SPI_SCPOL_INACTIVE_IS_HIGH (1) 237 /** 238 * @} 239 */ 240 241 /** @defgroup USI_SPI_SCPH_definitions 242 * @{ 243 */ 244 #define USI_SPI_SCPH_TOGGLES_IN_MIDDLE (0) 245 #define USI_SPI_SCPH_TOGGLES_AT_START (1) 246 /** 247 * @} 248 */ 249 250 /** @defgroup USI_SPI_SS_Toggle_Phase_definitions 251 * @{ 252 */ 253 #define USI_SPI_SS_NOT_TOGGLE (0) 254 #define USI_SPI_SS_TOGGLE (1) 255 /** 256 * @} 257 */ 258 259 260 /** @defgroup USI_SPI_Data_Frame_Size_definitions 261 * @{ 262 */ 263 #define USI_SPI_DFS_4_BITS (3) 264 #define USI_SPI_DFS_5_BITS (4) 265 #define USI_SPI_DFS_6_BITS (5) 266 #define USI_SPI_DFS_7_BITS (6) 267 #define USI_SPI_DFS_8_BITS (7) 268 #define USI_SPI_DFS_9_BITS (8) 269 #define USI_SPI_DFS_10_BITS (9) 270 #define USI_SPI_DFS_11_BITS (10) 271 #define USI_SPI_DFS_12_BITS (11) 272 #define USI_SPI_DFS_13_BITS (12) 273 #define USI_SPI_DFS_14_BITS (13) 274 #define USI_SPI_DFS_15_BITS (14) 275 #define USI_SPI_DFS_16_BITS (15) 276 /** 277 * @} 278 */ 279 280 /** @defgroup USI_SPI_ROLE_definitions 281 * @{ 282 */ 283 #define USI_SPI_SLAVE (0) 284 #define USI_SPI_MASTER (1) 285 /** 286 * @} 287 */ 288 289 /** @defgroup USI_SPI_DMA_Control_definitions 290 * @{ 291 */ 292 #define USI_SPI_NODMA (0) 293 #define USI_SPI_RXDMA_ENABLE (1) 294 #define USI_SPI_TXDMA_ENABLE (2) 295 #define USI_SPI_TRDMA_ENABLE (3) 296 /** 297 * @} 298 */ 299 300 /** @defgroup USI_SPI_FIFO_depth_definitions 301 * @{ 302 */ 303 #define USI_SPI_TX_FIFO_DEPTH (64) 304 #define USI_SPI_RX_FIFO_DEPTH (64) 305 /** 306 * @} 307 */ 308 309 /** @defgroup USI_SPI_Interrupt_definitions 310 * @{ 311 */ 312 #define USI_SPI_INTERRUPT_MASK (USI_TXFIFO_ALMOST_EMTY_INTR_EN | \ 313 USI_TXFIFO_OVERFLOW_INTR_EN | \ 314 USI_TXFIFO_UNDERFLOW_INTR_EN | \ 315 USI_RXFIFO_ALMOST_FULL_INTR_EN | \ 316 USI_RXFIFO_OVERFLOW_INTR_EN | \ 317 USI_RXFIFO_UNDERFLOW_INTR_EN | \ 318 USI_SPI_RX_DATA_FRM_ERR_INTER_EN) 319 320 #define USI_SPI_INTERRUPT_CLEAR_MASK (USI_TXFIFO_OVERFLOW_CLR | \ 321 USI_TXFIFO_UNDERFLOW_CLR | \ 322 USI_RXFIFO_OVERFLOW_CLR | \ 323 USI_RXFIFO_UNDERFLOW_CLR | \ 324 USI_SPI_RX_DATA_FRM_ERR_CLR) 325 /** 326 * @} 327 */ 328 329 /** @defgroup USI_TRX_Threshold_Level_definitions 330 * @{ 331 */ 332 #define IS_USI_SPI_RxThresholdLevel(value) (value <= 63) 333 #define IS_USI_SPI_TxThresholdLevel(value) (value <= 63) 334 /** 335 * @} 336 */ 337 338 /** @defgroup USI_TRX_DMA_Level_definitions 339 * @{ 340 */ 341 #define IS_USI_SPI_RxDMALevel(value) (value <= 63) 342 #define IS_USI_SPI_TxDMALevel(value) (value <= 63) 343 /** 344 * @} 345 */ 346 347 348 /** 349 * @} 350 */ 351 352 /* Exported functions --------------------------------------------------------*/ 353 /** @defgroup USI_SPI_Exported_Functions USI-SPI Exported Functions 354 * @{ 355 */ 356 /** @defgroup USI_SPI_Exported_Normal_Functions USI-SPI Exported Normal Functions 357 * @{ 358 */ 359 _LONG_CALL_ void USI_SSI_StructInit(USI_SSI_InitTypeDef* USI_SSI_InitStruct); 360 _LONG_CALL_ void USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct); 361 _LONG_CALL_ void USI_SSI_Cmd(USI_TypeDef *usi_dev, u32 NewStatus); 362 _LONG_CALL_ void USI_SSI_TRxPath_Cmd(USI_TypeDef *usi_dev, u32 path, u32 NewStatus); 363 _LONG_CALL_ u32 USI_SSI_GetTRxPath(USI_TypeDef *usi_dev); 364 _LONG_CALL_ void USI_SSI_INTConfig(USI_TypeDef* usi_dev, u32 USI_SSI_IT, u32 newState); 365 _LONG_CALL_ void USI_SSI_SetSclkPolarity(USI_TypeDef *usi_dev, u32 SclkPolarity); 366 _LONG_CALL_ void USI_SSI_SetSclkPhase(USI_TypeDef *usi_dev, u32 SclkPhase); 367 _LONG_CALL_ void USI_SSI_SetSSTogglePhase(USI_TypeDef *usi_dev, u32 TogglePhase); 368 _LONG_CALL_ void USI_SSI_SetDataFrameSize(USI_TypeDef *usi_dev, u32 DataFrameSize); 369 _LONG_CALL_ void USI_SSI_SetSampleDelay(USI_TypeDef *usi_dev, u32 SampleDelay); 370 _LONG_CALL_ void USI_SSI_SetReadLen(USI_TypeDef *usi_dev, u32 DataFrameNumber); 371 _LONG_CALL_ void USI_SSI_SetBaudDiv(USI_TypeDef *usi_dev, u32 ClockDivider); 372 _LONG_CALL_ void USI_SSI_SetBaud(USI_TypeDef *USIx, u32 BaudRate, u32 IpClk); 373 _LONG_CALL_ void USI_SSI_SetIsrClean(USI_TypeDef *usi_dev, u32 InterruptStatus); 374 _LONG_CALL_ void USI_SSI_WriteData(USI_TypeDef *usi_dev, u32 value); 375 _LONG_CALL_ void USI_SSI_SetRxFifoLevel(USI_TypeDef *usi_dev, u32 RxThresholdLevel); 376 _LONG_CALL_ void USI_SSI_SetTxFifoLevel(USI_TypeDef *usi_dev, u32 TxThresholdLevel); 377 _LONG_CALL_ u32 USI_SSI_Writeable(USI_TypeDef *usi_dev); 378 _LONG_CALL_ u32 USI_SSI_Writeable(USI_TypeDef *usi_dev); 379 _LONG_CALL_ u32 USI_SSI_ReadData(USI_TypeDef *usi_dev); 380 _LONG_CALL_ u32 USI_SSI_ReceiveData(USI_TypeDef *usi_dev, void* RxData, u32 Length); 381 _LONG_CALL_ u32 USI_SSI_SendData(USI_TypeDef *usi_dev, void* TxData, u32 Length, u32 Role); 382 _LONG_CALL_ u32 USI_SSI_GetRxCount(USI_TypeDef *usi_dev); 383 _LONG_CALL_ u32 USI_SSI_GetTxCount(USI_TypeDef *usi_dev); 384 _LONG_CALL_ u32 USI_SSI_GetTxFIFOStatus(USI_TypeDef *usi_dev); 385 _LONG_CALL_ u32 USI_SSI_GetRxFIFOStatus(USI_TypeDef *usi_dev); 386 _LONG_CALL_ u32 USI_SSI_GetTransStatus(USI_TypeDef *usi_dev); 387 _LONG_CALL_ u32 USI_SSI_GetDataFrameSize(USI_TypeDef *usi_dev); 388 _LONG_CALL_ u32 USI_SSI_Busy(USI_TypeDef *usi_dev); 389 _LONG_CALL_ u32 USI_SSI_GetIsr(USI_TypeDef *usi_dev); 390 _LONG_CALL_ u32 USI_SSI_GetRawIsr(USI_TypeDef *usi_dev); 391 392 /** 393 * @} 394 */ 395 396 /** @defgroup USI_SPI_Exported_DMA_Functions USI-SPI Exported DMA Functions 397 * @{ 398 */ 399 _LONG_CALL_ BOOL USI_SSI_TXGDMA_Init(u32 Index, PGDMA_InitTypeDef GDMA_InitStruct, void *CallbackData, 400 IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length); 401 _LONG_CALL_ BOOL USI_SSI_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, 402 IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length); 403 _LONG_CALL_ void USI_SSI_SetDmaEnable(USI_TypeDef *usi_dev, u32 newState, u32 Mask); 404 _LONG_CALL_ void USI_SSI_SetDmaLevel(USI_TypeDef *usi_dev, u32 TxLevel, u32 RxLevel); 405 /** 406 * @} 407 */ 408 409 /** 410 * @} 411 */ 412 413 /** 414 * @} 415 */ 416 417 /** 418 * @} 419 */ 420 421 /* Other Definitions --------------------------------------------------------*/ 422 423 #endif //_RTL8721D_USI_SSI_H_ 424 425 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 426