1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef __REG_DMA_H__ 5 #define __REG_DMA_H__ 6 7 #include "plat_types.h" 8 #include "stdint.h" 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #define XDMA_NUMBER_CHANNELS 16 15 16 // DMA Channel register block structure 17 struct XDMA_CH_T { 18 __IO uint32_t DADR; // 0x200+N*0x10 DMA Descriptor Address Registers 0-15 19 __IO uint32_t SADR; // 0x204+N*0x10 DMA Source Address Registers 0-15 20 __IO uint32_t TADR; // 0x208+N*0x10 DMA Target Address Registers 0-15 21 __IO uint32_t CMD; // 0x20C+N*0x10 DMA Command Registers 0-15 22 }; 23 24 struct XDMA_CH_H_T { 25 __IO uint32_t DADRH; // 0x300+N*0x10 DMA Descriptor Address Higher Bits Registers 0-15 26 __IO uint32_t SADRH; // 0x304+N*0x10 DMA Source Address Higher Bits Registers 0-15 27 __IO uint32_t TADRH; // 0x308+N*0x10 DMA Target Address Higher Bits Registers 0-15 28 __IO uint32_t DBG; // 0x30C+N*0x10 DMA debug port 29 }; 30 31 // DMA register block 32 struct XDMA_T { 33 __IO uint32_t DCSR[XDMA_NUMBER_CHANNELS]; // Offset: 0x00-0x3C DMA Channel Control/Status Registers 0-15 34 uint32_t RESERVED0[24]; // Offset: 0x40 35 __IO uint32_t ALGN; // Offset: 0xA0 DMA Alignment Register 36 __IO uint32_t PCSR; // Offset: 0xA4 DMA Programmed I/O Control Status Register 37 uint32_t RESERVED1[14]; // Offset: 0xA8 38 __IO uint32_t RQSR; // Offset: 0xE0 DREQ Status Register 0 39 uint32_t RESERVED2[3]; // Offset: 0xE4 40 __I uint32_t INTSTAT; // Offset: 0xF0 DMA Interrupt Register 41 uint32_t RESERVED3[3]; // Offset: 0xF4 42 __IO uint32_t RCMR[52]; // Offset: 0x0100-0x01CC DMA Request to Channel Map Registers 0-51 43 uint32_t RESERVED4[12]; // Offset: 0x01D0 44 struct XDMA_CH_T CH[XDMA_NUMBER_CHANNELS]; // Offset: 0x200-0x2x0 DMA Descriptor Address Registers 0-15 45 struct XDMA_CH_H_T CH_H[XDMA_NUMBER_CHANNELS]; // Offset: 0x300-0x3F0 DMA Descriptor Address Higher Bits Registers 0-15 46 }; 47 48 //Offset: 0x00 - 0x3C 49 #define XDMA_CONFIG_RUN (((0x1) << 31)) // software to start or stop the channel 50 #define XDMA_CONFIG_NODESCFETCH(n) ((((n) & 0x1) << 30)) // This bit controls whether or not a channel has a descriptor 51 #define XDMA_CONFIG_STOPIRQEN(n) ((((n) & 0x1) << 29)) // Stop interrupt enabled 52 #define XDMA_CONFIG_EORIRQEN(n) ((((n) & 0x1) << 28)) // Setting the End-of-Receive interrupt enable 53 #define XDMA_CONFIG_EORJMPEN(n) ((((n) & 0x1) << 27)) // Jump to the next descriptor on EOR 54 #define XDMA_CONFIG_EORSTOPEN(n) ((((n) & 0x1) << 26)) // Stop channel on EOR 55 #define XDMA_CONFIG_SETCMPST(n) ((((n) & 0x1) << 25)) // Set descriptor compare status 56 #define XDMA_CONFIG_CLRCMPST(n) ((((n) & 0x1) << 24)) // Clear descriptor compare status 57 #define XDMA_CONFIG_RASIRQEN(n) ((((n) & 0x1) << 23)) // Request after channel stopped interrupt enable 58 #define XDMA_CONFIG_MASKRUN(n) ((((n) & 0x1) << 22)) // Mask <Run> during a programmed I/O write to this register 59 #define XDMA_CONFIG_LPAE_EN ((0x1 << 21)) // Long Physical Address Extension enable 60 #define XDMA_CONFIG_EORINT(n) ((((n) & 0x1) << 9)) // End of Receive Interrupt 61 #define XDMA_CONFIG_RASINTR(n) ((((n) & 0x1) << 4)) // Request after channel stopped 62 #define XDMA_STA_STOPINTR ((0x1 << 3)) // Stop interrupt 63 #define XDMA_STA_ENDINTR ((0x1 << 2)) // End interrupt 64 #define XDMA_STA_STARTINTR ((0x1 << 1)) // Start interrupt 65 #define XDMA_STA_BUSERRINTR ((0x1 << 0)) // Bus error interrupt 66 67 //Offset: 0xA0 68 #define XDMA_CONFIG_DALGN(n) ((0x1 << n)) // Alignment control for channel x 69 70 //Offset: 0xE0 71 #define XDMA_CONFIG_CLR ((0x1 << 8)) // Clearing pending request 72 73 //Offset: 0x0100-0x01CC 74 #define XDMA_CONFIG_MAPVLD(n) ((((n) & 0x1) << 7)) // Map valid channel 75 #define XDMA_CONFIG_CHLNUM(n) ((((n) & 0x1F) << 0)) // Channel number 76 77 // Macro defines for DMA channel command registers 78 79 //Offset: 0x200-0x2x0 80 #define XDMA_CONFIG_DESCRIPTOR_ADDRESS(n) ((((n) & 0xFFFFFFF) << 4)) // Contains address of next descriptor 81 #define XDMA_CONFIG_DESCRIPTOR_BREN(n) ((((n) & 0x1) << 1)) // Enable Descriptor Branch 82 #define XDMA_CONFIG_DESCRIPTOR_STOP(n) ((((n) & 0x1) << 0)) // Stop 83 84 //Offset: 0x204-0x2x4 85 #define XDMA_CONFIG_SRCADDR(n) ((((n) & 0x1FFFFFFF) << 3)) // Source address 86 #define XDMA_CONFIG_SRCADDR2(n) ((((n) & 0x1) << 2)) // 87 #define XDMA_CONFIG_SRCADDR0(n) ((((n) & 0x3) << 0)) // 88 89 //Offset: 0x208-0x2x8 90 #define XDMA_CONFIG_TRGADDR(n) ((((n) & 0x1FFFFFFF) << 3)) // Target address 91 #define XDMA_CONFIG_TRGADDR2(n) ((((n) & 0x1) << 2)) // 92 #define XDMA_CONFIG_TRGADDR0(n) ((((n) & 0x3) << 0)) // 93 94 //Offset: 0x20C-0x2xC 95 #define XDMA_CONTROL_SI ((1UL << 31)) // Source increment 96 #define XDMA_CONTROL_DI ((1UL << 30)) // Destination increment 97 #define XDMA_CONTROL_SFLOW ((1UL << 29)) // Source flow control 98 #define XDMA_CONTROL_DFLOW ((1UL << 28)) // Destination flow control 99 #define XDMA_CONTROL_DCMP_ENABLE ((1UL << 25)) // Descriptor compare enable 100 #define XDMA_CONTROL_ADDRMODE(n) ((((n) & 0x01) << 23)) // transfer width 101 #define XDMA_CONTROL_STARTIRQEN ((1UL << 22)) // Start interrupt enable 102 #define XDMA_CONTROL_ENDIRQEN ((1UL << 21)) // End interrupt enable 103 #define XDMA_CONTROL_MAXBSIZE(n) ((((n) & 0x07) << 16)) // MAX burst size 104 #define XDMA_CONTROL_WIDTH(n) ((((n) & 0x03) << 14)) // transfer width 105 #define XDMA_CONTROL_WIDTH_MASK (0x03 << 14) 106 #define XDMA_CONTROL_WIDTH_SHIFT (14) 107 #define XDMA_CONTROL_TRANSFERSIZE(n) ((((n) & 0x1FFF) << 0)) // Transfer size 108 #define XDMA_CONTROL_TRANSFERSIZE_MASK (0x1FFF << 0) 109 #define XDMA_CONTROL_TRANSFERSIZE_SHIFT (0) 110 111 #define XDMA_CONTROL_DESCRIPTOR_ADDRESS_H(n) ((((n) & 0xFF) << 0)) // contrain the higher 8 bits of memory address of the next descriptor 112 #define XDMA_CONTROL_SOURCE_ADDRESS_H(n) ((((n) & 0xFF) << 0)) // contrain the source address higher bits [39:32] of the current descriptor 113 #define XDMA_CONTROL_TARGET_ADDRESS_H(n) ((((n) & 0xFF) << 0)) // contrain the target address higher bits [39:32] of the current descriptor 114 115 /* 116 #define XDMA_CONTROL_SRCAHB1 0 117 #define XDMA_CONTROL_DSTAHB1 0 118 #define XDMA_CONTROL_PROT1 ((1UL << 28)) // Indicates that the access is in user mode or privileged mode 119 #define XDMA_CONTROL_PROT2 ((1UL << 29)) // Indicates that the access is bufferable or not bufferable 120 #define XDMA_CONTROL_PROT3 ((1UL << 30)) // Indicates that the access is cacheable or not cacheable 121 #define XDMA_CONTROL_TC_IRQ ((1UL << 31)) // Terminal count interrupt enable bit 122 123 // Macro defines for DMA Channel Configuration registers 124 125 #define XDMA_CONFIG_EN ((1UL << 0)) // DMA control enable 126 #define XDMA_CONFIG_SRCPERIPH(n) ((((n) & 0x1F) << 1)) // Source peripheral 127 #define XDMA_CONFIG_DSTPERIPH(n) ((((n) & 0x1F) << 6)) // Destination peripheral 128 #define XDMA_CONFIG_TRANSFERTYPE(n) ((((n) & 0x7) << 11)) // This value indicates the type of transfer 129 #define XDMA_CONFIG_ERR_IRQMASK ((1UL << 14)) // Interrupt error mask 130 #define XDMA_CONFIG_TC_IRQMASK ((1UL << 15)) // Terminal count interrupt mask 131 #define XDMA_CONFIG_LOCK ((1UL << 16)) // Lock 132 #define XDMA_CONFIG_ACTIVE ((1UL << 17)) // Active 133 #define XDMA_CONFIG_HALT ((1UL << 18)) // Halt 134 #define XDMA_CONFIG_TRY_BURST ((1UL << 19)) // Try burst 135 */ 136 137 #define XDMA_INTSTA_CHAN (0xF) 138 #define XDMA_ERRINT_CHAN (0x1) 139 #define XDMA_STAT_CHAN_ALL (0xFF) 140 141 // Macro defines for DMA Configuration register 142 143 #define XDMA_DMACONFIG_EN (1 << 0) // DMA Controller enable 144 #define XDMA_DMACONFIG_AHB1_BIGENDIAN (1 << 1) // AHB Master endianness configuration 145 #define XDMA_DMACONFIG_AHB2_BIGENDIAN (1 << 2) // AHB Master endianness configuration 146 147 #define XDMA_DMACONFIG_TC_IRQ_EN(n) (((n) & 0xFF) << 4) 148 #define XDMA_DMACONFIG_TC_IRQ_EN_MASK (0xFF << 4) 149 #define XDMA_DMACONFIG_TC_IRQ_EN_SHIFT (4) 150 151 #ifdef __cplusplus 152 } 153 #endif 154 155 #endif 156 157