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/AliOS-Things-master/hardware/chip/smarth_rv64/smarth_rv64/include/
A Dck_usart.h67 __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */
75 __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */
78 __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */
79 __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */
81 __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */
A Ddw_gpio.h35 … __IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */
36 …__IM uint32_t RAWINTSTATUS; /* Offset: 0x014 (W/R) Raw interrupt status of Port…
39 …__IM uint32_t EXT_PORTA; /* Offset: 0x020 (W/R) PortA external port register…
40 …__IM uint32_t EXT_PORTB; /* Offset: 0x024 (W/R) PortB external port register…
/AliOS-Things-master/components/csi/CMSIS/Core/Include/
A Dcore_cm7.h462 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
477 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
484 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1152 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1288 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1290 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1292 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1299 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1300 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm4.h230 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
447 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
462 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1064 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1065 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1066 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1068 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1069 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1075 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1076 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm3.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1006 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1007 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1008 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1010 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1011 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1017 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1018 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_sc300.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm33.h286 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1188 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1313 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1476 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
A Dcore_cm35p.h286 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1188 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1313 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1476 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/third_party/cmsis/CMSIS/Core/Include/
A Dcore_cm7.h462 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
477 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
484 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1155 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1291 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1293 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1295 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1302 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1303 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm4.h230 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
447 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
462 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1064 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1065 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1066 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1068 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1069 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1075 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1076 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm3.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1006 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1007 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1008 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1010 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1011 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1017 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1018 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_sc300.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm33.h286 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1188 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1313 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1476 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/tensorflow/lite/micro/tools/make/downloads/cmsis/CMSIS/Core/Include/
A Dcore_cm7.h462 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
477 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
484 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1155 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1291 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1293 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1295 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1302 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1303 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm4.h230 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
447 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
462 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1064 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1065 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1066 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1068 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1069 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1075 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1076 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm3.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1006 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1007 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1008 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1010 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1011 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1017 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1018 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_sc300.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/cmsis/inc/
A Dcore_sc300.h173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm4.h228 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
446 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
461 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1063 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1064 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1065 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1067 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1068 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1074 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1075 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm3.h173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1001 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1002 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1003 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1005 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1006 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1012 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1013 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm7.h457 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
472 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
479 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1146 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1282 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1284 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1286 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1293 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1294 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
/AliOS-Things-master/components/py_engine/engine/lib/cmsis/inc/
A Dcore_sc300.h173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm4.h225 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
442 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
457 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1059 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1060 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1061 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1063 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1064 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1070 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1071 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm3.h173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1001 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1002 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1003 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1005 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1006 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1012 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1013 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm7.h457 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
472 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
479 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1146 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1282 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1284 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1286 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1293 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1294 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]

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