Home
last modified time | relevance | path

Searched refs:__IO (Results 1 – 25 of 130) sorted by relevance

123456

/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Dhal_platform.h469 __IO uint8_t byte;
470 __IO uint16_t half;
471 __IO uint32_t word;
1387 __IO uint16_t RSVD5;
1391 __IO uint16_t RSVD7;
1395 __IO uint16_t RSVD9;
1396 __IO uint8_t RSVD10;
1400 __IO uint16_t RSVD11;
1402 __IO uint8_t RSVD13;
1409 __IO uint8_t RSVD16;
[all …]
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/hal/
A Dreg_sec_eng.h38 __IO uint32_t ADEC_CTRL; // 0x000
39 __IO uint32_t ADEC_CTRL2; // 0x004
40 __IO uint32_t RESERVED_00C; // 0x008
41 __IO uint32_t ADEC_INT; // 0x00C
42 __IO uint32_t ADEC_INT_MSK; // 0x010
43 __IO uint32_t ADEC_ERR_ADR; // 0x014
44 __IO uint32_t RESERVED_018; // 0x018
48 __IO uint32_t DMA_CTRL; // 0x000
49 __IO uint32_t DMA_TDL; // 0x004
50 __IO uint32_t DMA_RDL; // 0x008
[all …]
A Dreg_psramuhs_mc.h10 __IO uint32_t REG_000;
11 __IO uint32_t REG_004;
12 __IO uint32_t REG_008;
13 __IO uint32_t REG_00C;
14 __IO uint32_t REG_010;
15 __IO uint32_t REG_014;
16 __IO uint32_t REG_018;
17 __IO uint32_t REG_01C;
18 __IO uint32_t REG_020;
19 __IO uint32_t REG_024;
[all …]
A Dreg_psram_mc_v2.h10 __IO uint32_t REG_000;
11 __IO uint32_t REG_004;
12 __IO uint32_t REG_008;
13 __IO uint32_t REG_00C;
14 __IO uint32_t REG_010;
15 __IO uint32_t REG_014;
16 __IO uint32_t REG_018;
17 __IO uint32_t REG_01C;
18 __IO uint32_t REG_020;
19 __IO uint32_t REG_024;
[all …]
A Dreg_norflaship_v2.h10 __IO uint32_t REG_000;
11 __IO uint32_t REG_004;
17 __IO uint32_t REG_00C;
18 __IO uint32_t REG_010;
19 __IO uint32_t REG_014;
20 __IO uint32_t REG_018;
21 __IO uint32_t REG_01C;
22 __IO uint32_t REG_020;
23 __IO uint32_t REG_024;
24 __IO uint32_t REG_028;
[all …]
A Dreg_psram_phy_v2.h10 __IO uint32_t REG_000;
11 __IO uint32_t REG_004;
12 __IO uint32_t REG_008;
13 __IO uint32_t REG_00C;
14 __IO uint32_t REG_010;
15 __IO uint32_t REG_014;
16 __IO uint32_t REG_018;
17 __IO uint32_t REG_01C;
18 __IO uint32_t REG_020;
19 __IO uint32_t REG_024;
[all …]
A Dreg_usb.h26 __IO uint32_t GOTGCTL; //0x00000000
27 __IO uint32_t GOTGINT; //0x00000004
1634 __IO uint32_t USBIF_00;
1635 __IO uint32_t USBIF_04;
1636 __IO uint32_t USBIF_08;
1637 __IO uint32_t USBIF_0C;
1638 __IO uint32_t USBIF_10;
1639 __IO uint32_t USBIF_14;
1640 __IO uint32_t USBIF_18;
1641 __IO uint32_t USBIF_1C;
[all …]
A Dreg_dma.h19 __IO uint32_t SRCADDR; // 0x100+N*0x20 DMA Channel Source Address Register
22 __IO uint32_t CONTROL; // 0x10C+N*0x20 DMA Channel Control Register
23 __IO uint32_t CONFIG; // 0x110+N*0x20 DMA Channel Configuration Register
28 __IO uint32_t SRCX; // 0x200+N*0x20 DMA 2D Source X Axis Register
29 __IO uint32_t SRCY; // 0x204+N*0x20 DMA 2D Source Y Axis Register
30 __IO uint32_t DSTX; // 0x208+N*0x20 DMA 2D Destination X Axis Register
32 __IO uint32_t CTRL; // 0x210+N*0x20 DMA 2D Control Register
46 __IO uint32_t SOFTBREQ; // 0x020 DMA Software Burst Request Register
47 __IO uint32_t SOFTSREQ; // 0x024 DMA Software Single Request Register
50 __IO uint32_t DMACONFIG; // 0x030 DMA Configuration Register
[all …]
A Dreg_transq.h13 __IO uint32_t CTRL; // 0x000
14 __IO uint32_t RMT_INTMASK; // 0x004
15 __IO uint32_t RMT_INTSET; // 0x008
16 __IO uint32_t LDONE_INTMASK; // 0x00C
21 __IO uint32_t LERR_INTMASK; // 0x014
26 __IO uint32_t RESERVED_01C; // 0x01C
29 __IO uint32_t RESERVED_028[2]; // 0x028
31 __IO uint32_t ADDR; // 0x030 + N * 8
34 __IO uint32_t RESERVED_130[0x34]; // 0x130
39 __IO uint32_t RMT_MIS; // 0x204
[all …]
A Dreg_pwm.h13 __IO uint32_t EN; // 0x004
14 __IO uint32_t INV; // 0x008
15 __IO uint32_t PHASE01; // 0x00C
16 __IO uint32_t PHASE23; // 0x010
17 __IO uint32_t LOAD01; // 0x014
18 __IO uint32_t LOAD23; // 0x018
19 __IO uint32_t TOGGLE01; // 0x01C
20 __IO uint32_t TOGGLE23; // 0x020
21 __IO uint32_t PHASEMOD; // 0x024
22 __IO uint32_t ST1_23; // 0x028
[all …]
A Dreg_xdma.h18 __IO uint32_t DADR; // 0x200+N*0x10 DMA Descriptor Address Registers 0-15
19 __IO uint32_t SADR; // 0x204+N*0x10 DMA Source Address Registers 0-15
20 __IO uint32_t TADR; // 0x208+N*0x10 DMA Target Address Registers 0-15
21 __IO uint32_t CMD; // 0x20C+N*0x10 DMA Command Registers 0-15
25 …__IO uint32_t DADRH; // 0x300+N*0x10 DMA Descriptor Address Higher Bits Registers…
26 …__IO uint32_t SADRH; // 0x304+N*0x10 DMA Source Address Higher Bits Registers 0-15
27 …__IO uint32_t TADRH; // 0x308+N*0x10 DMA Target Address Higher Bits Registers 0-15
28 __IO uint32_t DBG; // 0x30C+N*0x10 DMA debug port
35 __IO uint32_t ALGN; // Offset: 0xA0 DMA Alignment Register
36 …__IO uint32_t PCSR; // Offset: 0xA4 DMA Programmed I/O Control Status R…
[all …]
A Dreg_uart.h11 __IO uint32_t UARTDR; // 0x000
19 __IO uint32_t UARTILPR; // 0x020
20 __IO uint32_t UARTIBRD; // 0x024
21 __IO uint32_t UARTFBRD; // 0x028
22 __IO uint32_t UARTLCR_H; // 0x02C
23 __IO uint32_t UARTCR; // 0x030
24 __IO uint32_t UARTIFLS; // 0x034
25 __IO uint32_t UARTIMSC; // 0x038
29 __IO uint32_t UARTDMACR; // 0x048
A Dreg_spi.h11 __IO uint32_t SSPCR0; //0x00000000
12 __IO uint32_t SSPCR1; //0x00000004
13 __IO uint32_t SSPDR; //0x00000008
15 __IO uint32_t SSPCPSR; //0x00000010
16 __IO uint32_t SSPIMSC; //0x00000014
20 __IO uint32_t SSPDMACR; //0x00000024
22 __IO uint32_t SSPRXCR; //0x00000088
A Dreg_trng.h12 __IO uint32_t RNG_IMR; // 0x100
15 __IO uint32_t TRNG_CONFIG; // 0x10C
18 __IO uint32_t RND_SOURCE_ENABLE; //0x12c
19 __IO uint32_t SAMPLE_CNT1; //0x130
20 __IO uint32_t AUTOCORR_STATISTIC; //0x134
A Dreg_rtc.h13 __IO uint32_t RTCMR; // 0x004
14 __IO uint32_t RTCLR; // 0x008
15 __IO uint32_t RTCCR; // 0x00C
16 __IO uint32_t RTCIMSC; // 0x010
A Dreg_timer.h14 __IO uint32_t Load; /* Offset: 0x000 (R/W) Timer X Load */
16 __IO uint32_t Control; /* Offset: 0x008 (R/W) Timer X Control */
20 __IO uint32_t BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
24 __IO uint32_t ElapsedCtrl;
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/hal/haas1000/
A Dreg_codec_haas1000.h10 __IO uint32_t REG_000;
11 __IO uint32_t REG_004;
12 __IO uint32_t REG_008;
13 __IO uint32_t REG_00C;
14 __IO uint32_t REG_010;
15 __IO uint32_t REG_014;
16 __IO uint32_t REG_018;
17 __IO uint32_t REG_01C;
18 __IO uint32_t REG_020;
19 __IO uint32_t REG_024;
[all …]
A Dreg_cmu_haas1000.h10 __IO uint32_t HCLK_ENABLE; // 0x00
11 __IO uint32_t HCLK_DISABLE; // 0x04
12 __IO uint32_t PCLK_ENABLE; // 0x08
13 __IO uint32_t PCLK_DISABLE; // 0x0C
14 __IO uint32_t OCLK_ENABLE; // 0x10
15 __IO uint32_t OCLK_DISABLE; // 0x14
16 __IO uint32_t HCLK_MODE; // 0x18
17 __IO uint32_t PCLK_MODE; // 0x1C
18 __IO uint32_t OCLK_MODE; // 0x20
19 __IO uint32_t RESERVED_024; // 0x24
[all …]
A Dreg_btcmu_haas1000.h10 __IO uint32_t CLK_ENABLE; // 0x00
11 __IO uint32_t CLK_DISABLE; // 0x04
12 __IO uint32_t CLK_MODE; // 0x08
13 __IO uint32_t DIV_TIMER; // 0x0C
14 __IO uint32_t RESET_SET; // 0x10
15 __IO uint32_t RESET_CLR; // 0x14
16 __IO uint32_t DIV_WDT; // 0x18
17 __IO uint32_t RESET_PULSE; // 0x1C
19 __IO uint32_t CLK_OUT; // 0x44
21 __IO uint32_t ISIRQ_SET; // 0x50
[all …]
A Dreg_iomux_haas1000.h10 __IO uint32_t REG_000;
11 __IO uint32_t REG_004;
12 __IO uint32_t REG_008;
13 __IO uint32_t REG_00C;
14 __IO uint32_t REG_010;
15 __IO uint32_t REG_014;
16 __IO uint32_t REG_018;
17 __IO uint32_t REG_01C;
18 __IO uint32_t REG_020;
19 __IO uint32_t REG_024;
[all …]
A Dreg_aoncmu_haas1000.h11 __IO uint32_t TOP_CLK_ENABLE; // 0x04
12 __IO uint32_t TOP_CLK_DISABLE; // 0x08
13 __IO uint32_t RESET_PULSE; // 0x0C
14 __IO uint32_t RESET_SET; // 0x10
15 __IO uint32_t RESET_CLR; // 0x14
16 __IO uint32_t CLK_SELECT; // 0x18
17 __IO uint32_t CLK_OUT; // 0x1C
18 __IO uint32_t WRITE_UNLOCK; // 0x20
19 __IO uint32_t MEMSC[4]; // 0x24
21 __IO uint32_t BOOTMODE; // 0x38
[all …]
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/cmsis/
A Dcore_cm3.h186 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
301 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
561 …__IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
595 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist…
596 …__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register …
597 …__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register …
892 …__IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regist…
896 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
908 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
910 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
[all …]
A Dcore_cm4.h222 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
338 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
625 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist…
626 …__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register …
627 …__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register …
922 …__IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regist…
926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
929 …__IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regis…
938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
[all …]
A Dcore_cm0plus.h179 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
293 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
295 …__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
297 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
299 …__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
302 …__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register …
433 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist…
434 …__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register …
435 …__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register …
484 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register …
[all …]
A Dcore_cm0.h169 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
282 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
284 …__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
286 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
288 …__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
291 …__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register …
308 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
310 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
412 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist…
413 …__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register …
[all …]

Completed in 92 milliseconds

123456