1 /* ========================================================================== 2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $ 3 * $Revision: #15 $ 4 * $Date: 2012/12/10 $ 5 * $Change: 2123206 $ 6 * 7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, 8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless 9 * otherwise expressly agreed to in writing between Synopsys and you. 10 * 11 * The Software IS NOT an item of Licensed Software or Licensed Product under 12 * any End User Software License Agreement or Agreement for Licensed Product 13 * with Synopsys or any supplement thereto. You are permitted to use and 14 * redistribute this Software in source and binary forms, with or without 15 * modification, provided that redistributions of source code must retain this 16 * notice. You may not view, use, disclose, copy or distribute this file or 17 * any information contained herein except pursuant to this license grant from 18 * Synopsys. If you do not agree with this notice, including the disclaimer 19 * below, then you are not authorized to use the Software. 20 * 21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 * ========================================================================== */ 33 #if !defined(__DWC_CORE_IF_H__) 34 #define __DWC_CORE_IF_H__ 35 36 #include "ameba_otg.h" 37 #include "dwc_os.h" 38 39 /** @file 40 * This file defines DWC_OTG Core API 41 */ 42 43 struct dwc_otg_core_if; 44 typedef struct dwc_otg_core_if dwc_otg_core_if_t; 45 46 /** Maximum number of Periodic FIFOs */ 47 #define MAX_PERIO_FIFOS 15 48 /** Maximum number of Periodic FIFOs */ 49 #define MAX_TX_FIFOS 15 50 51 /** Maximum number of Endpoints/HostChannels */ 52 #define MAX_EPS_CHANNELS 8 53 54 extern _LONG_CALL_ dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr, int mode); 55 extern _LONG_CALL_ void dwc_otg_core_init(dwc_otg_core_if_t * _core_if); 56 extern _LONG_CALL_ void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if); 57 58 extern _LONG_CALL_ void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if); 59 extern _LONG_CALL_ void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if); 60 61 extern _LONG_CALL_ uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if); 62 extern _LONG_CALL_ uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if); 63 64 extern _LONG_CALL_ uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if); 65 66 /** This function should be called on every hardware interrupt. */ 67 extern _LONG_CALL_ int32_t dwc_otg_handle_common_intr(void *otg_dev); 68 69 /** @name OTG Core Parameters */ 70 /** @{ */ 71 72 /** 73 * Specifies the OTG capabilities. The driver will automatically 74 * detect the value for this parameter if none is specified. 75 * 0 - HNP and SRP capable (default) 76 * 1 - SRP Only capable 77 * 2 - No HNP/SRP capable 78 */ 79 extern _LONG_CALL_ int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val); 80 extern _LONG_CALL_ int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if); 81 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 82 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 83 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 84 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 85 86 extern _LONG_CALL_ int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val); 87 extern _LONG_CALL_ int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if); 88 #define dwc_param_opt_default 1 89 90 /** 91 * Specifies whether to use slave or DMA mode for accessing the data 92 * FIFOs. The driver will automatically detect the value for this 93 * parameter if none is specified. 94 * 0 - Slave 95 * 1 - DMA (default, if available) 96 */ 97 extern _LONG_CALL_ int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, 98 int32_t val); 99 extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if); 100 #define dwc_param_dma_enable_default 1 101 102 /** 103 * When DMA mode is enabled specifies whether to use 104 * address DMA or DMA Descritor mode for accessing the data 105 * FIFOs in device mode. The driver will automatically detect 106 * the value for this parameter if none is specified. 107 * 0 - address DMA 108 * 1 - DMA Descriptor(default, if available) 109 */ 110 extern _LONG_CALL_ int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, 111 int32_t val); 112 extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if); 113 #define dwc_param_dma_desc_enable_default 1 114 115 /** The DMA Burst size (applicable only for External DMA 116 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) 117 */ 118 extern _LONG_CALL_ int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, 119 int32_t val); 120 extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if); 121 #define dwc_param_dma_burst_size_default 32 122 123 /** 124 * Specifies the maximum speed of operation in host and device mode. 125 * The actual speed depends on the speed of the attached device and 126 * the value of phy_type. The actual speed depends on the speed of the 127 * attached device. 128 * 0 - High Speed (default) 129 * 1 - Full Speed 130 */ 131 extern _LONG_CALL_ int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val); 132 extern _LONG_CALL_ int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if); 133 #if !defined(USB_DEV_FULL_SPEED) 134 #define dwc_param_speed_default 0 135 #else 136 #define dwc_param_speed_default 1 137 #endif 138 139 #define DWC_SPEED_PARAM_HIGH 0 140 #define DWC_SPEED_PARAM_FULL 1 141 142 /** Specifies whether low power mode is supported when attached 143 * to a Full Speed or Low Speed device in host mode. 144 * 0 - Don't support low power mode (default) 145 * 1 - Support low power mode 146 */ 147 extern _LONG_CALL_ int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * 148 core_if, int32_t val); 149 extern _LONG_CALL_ int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t 150 * core_if); 151 #define dwc_param_host_support_fs_ls_low_power_default 0 152 153 /** Specifies the PHY clock rate in low power mode when connected to a 154 * Low Speed device in host mode. This parameter is applicable only if 155 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 156 * then defaults to 6 MHZ otherwise 48 MHZ. 157 * 158 * 0 - 48 MHz 159 * 1 - 6 MHz 160 */ 161 extern _LONG_CALL_ int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * 162 core_if, int32_t val); 163 extern _LONG_CALL_ int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * 164 core_if); 165 #define dwc_param_host_ls_low_power_phy_clk_default 0 166 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 167 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 168 169 /** 170 * 0 - Use cC FIFO size parameters 171 * 1 - Allow dynamic FIFO sizing (default) 172 */ 173 extern _LONG_CALL_ int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, 174 int32_t val); 175 extern _LONG_CALL_ int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * 176 core_if); 177 #define dwc_param_enable_dynamic_fifo_default 1 178 179 /** Total number of 4-byte words in the data FIFO memory. This 180 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic 181 * Tx FIFOs. 182 * 32 to 32768 (default 8192) 183 * Note: The total FIFO memory depth in the FPGA configuration is 8192. 184 */ 185 extern _LONG_CALL_ int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, 186 int32_t val); 187 extern _LONG_CALL_ int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if); 188 #define dwc_param_data_fifo_size_default 8192 189 190 /** Number of 4-byte words in the Rx FIFO in device mode when dynamic 191 * FIFO sizing is enabled. 192 * 16 to 32768 (default 1064) 193 */ 194 extern _LONG_CALL_ int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, 195 int32_t val); 196 extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if); 197 #define dwc_param_dev_rx_fifo_size_default 1064 198 199 /** Number of 4-byte words in the non-periodic Tx FIFO in device mode 200 * when dynamic FIFO sizing is enabled. 201 * 16 to 32768 (default 1024) 202 */ 203 extern _LONG_CALL_ int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * 204 core_if, int32_t val); 205 extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * 206 core_if); 207 #define dwc_param_dev_nperio_tx_fifo_size_default 1024 208 209 /** Number of 4-byte words in each of the periodic Tx FIFOs in device 210 * mode when dynamic FIFO sizing is enabled. 211 * 4 to 768 (default 256) 212 */ 213 extern _LONG_CALL_ int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, 214 int32_t val, int fifo_num); 215 extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * 216 core_if, int fifo_num); 217 #define dwc_param_dev_perio_tx_fifo_size_default 256 218 219 /** Number of 4-byte words in the Rx FIFO in host mode when dynamic 220 * FIFO sizing is enabled. 221 * 16 to 32768 (default 1024) 222 */ 223 extern _LONG_CALL_ int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, 224 int32_t val); 225 extern _LONG_CALL_ int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if); 226 #define dwc_param_host_rx_fifo_size_default 1024 227 228 /** Number of 4-byte words in the non-periodic Tx FIFO in host mode 229 * when Dynamic FIFO sizing is enabled in the core. 230 * 16 to 32768 (default 1024) 231 */ 232 extern _LONG_CALL_ int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * 233 core_if, int32_t val); 234 extern _LONG_CALL_ int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * 235 core_if); 236 #define dwc_param_host_nperio_tx_fifo_size_default 1024 237 238 /** Number of 4-byte words in the host periodic Tx FIFO when dynamic 239 * FIFO sizing is enabled. 240 * 16 to 32768 (default 1024) 241 */ 242 extern _LONG_CALL_ int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * 243 core_if, int32_t val); 244 extern _LONG_CALL_ int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * 245 core_if); 246 #define dwc_param_host_perio_tx_fifo_size_default 1024 247 248 /** The maximum transfer size supported in bytes. 249 * 2047 to 65,535 (default 65,535) 250 */ 251 extern _LONG_CALL_ int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, 252 int32_t val); 253 extern _LONG_CALL_ int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if); 254 #define dwc_param_max_transfer_size_default 65535 255 256 /** The maximum number of packets in a transfer. 257 * 15 to 511 (default 511) 258 */ 259 extern _LONG_CALL_ int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, 260 int32_t val); 261 extern _LONG_CALL_ int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if); 262 #define dwc_param_max_packet_count_default 511 263 264 /** The number of host channel registers to use. 265 * 1 to 16 (default 12) 266 * Note: The FPGA configuration supports a maximum of 12 host channels. 267 */ 268 extern _LONG_CALL_ int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, 269 int32_t val); 270 extern _LONG_CALL_ int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if); 271 #define dwc_param_host_channels_default 12 272 273 /** The number of endpoints in addition to EP0 available for device 274 * mode operations. 275 * 1 to 15 (default 6 IN and OUT) 276 * Note: The FPGA configuration supports a maximum of 6 IN and OUT 277 * endpoints in addition to EP0. 278 */ 279 extern _LONG_CALL_ int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, 280 int32_t val); 281 extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if); 282 #define dwc_param_dev_endpoints_default 6 283 284 /** 285 * Specifies the type of PHY interface to use. By default, the driver 286 * will automatically detect the phy_type. 287 * 288 * 0 - Full Speed PHY 289 * 1 - UTMI+ (default) 290 * 2 - ULPI 291 */ 292 extern _LONG_CALL_ int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val); 293 extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if); 294 #define DWC_PHY_TYPE_PARAM_FS 0 295 #define DWC_PHY_TYPE_PARAM_UTMI 1 296 #define DWC_PHY_TYPE_PARAM_ULPI 2 297 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI 298 299 /** 300 * Specifies the UTMI+ Data Width. This parameter is 301 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 302 * PHY_TYPE, this parameter indicates the data width between 303 * the MAC and the ULPI Wrapper.) Also, this parameter is 304 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 305 * to "8 and 16 bits", meaning that the core has been 306 * configured to work at either data path width. 307 * 308 * 8 or 16 bits (default 16) 309 */ 310 extern _LONG_CALL_ int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, 311 int32_t val); 312 extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if); 313 #define dwc_param_phy_utmi_width_default 16 314 315 /** 316 * Specifies whether the ULPI operates at double or single 317 * data rate. This parameter is only applicable if PHY_TYPE is 318 * ULPI. 319 * 320 * 0 - single data rate ULPI interface with 8 bit wide data 321 * bus (default) 322 * 1 - double data rate ULPI interface with 4 bit wide data 323 * bus 324 */ 325 extern _LONG_CALL_ int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, 326 int32_t val); 327 extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if); 328 #define dwc_param_phy_ulpi_ddr_default 0 329 330 /** 331 * Specifies whether to use the internal or external supply to 332 * drive the vbus with a ULPI phy. 333 */ 334 extern _LONG_CALL_ int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, 335 int32_t val); 336 extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if); 337 #define DWC_PHY_ULPI_INTERNAL_VBUS 0 338 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1 339 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS 340 341 /** 342 * Specifies whether to use the I2Cinterface for full speed PHY. This 343 * parameter is only applicable if PHY_TYPE is FS. 344 * 0 - No (default) 345 * 1 - Yes 346 */ 347 extern _LONG_CALL_ int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, 348 int32_t val); 349 extern _LONG_CALL_ int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if); 350 #define dwc_param_i2c_enable_default 0 351 352 extern _LONG_CALL_ int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, 353 int32_t val); 354 extern _LONG_CALL_ int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if); 355 #define dwc_param_ulpi_fs_ls_default 0 356 357 extern _LONG_CALL_ int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val); 358 extern _LONG_CALL_ int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if); 359 #define dwc_param_ts_dline_default 0 360 361 /** 362 * Specifies whether dedicated transmit FIFOs are 363 * enabled for non periodic IN endpoints in device mode 364 * 0 - No 365 * 1 - Yes 366 */ 367 extern _LONG_CALL_ int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, 368 int32_t val); 369 extern _LONG_CALL_ int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * 370 core_if); 371 #define dwc_param_en_multiple_tx_fifo_default 1 372 373 /** Number of 4-byte words in each of the Tx FIFOs in device 374 * mode when dynamic FIFO sizing is enabled. 375 * 4 to 768 (default 256) 376 */ 377 //extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, 378 // int fifo_num, int32_t val); 379 extern _LONG_CALL_ int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val, 380 int fifo_num); 381 382 extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, 383 int fifo_num); 384 #define dwc_param_dev_tx_fifo_size_default 256 385 386 /** Thresholding enable flag- 387 * bit 0 - enable non-ISO Tx thresholding 388 * bit 1 - enable ISO Tx thresholding 389 * bit 2 - enable Rx thresholding 390 */ 391 extern _LONG_CALL_ int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val); 392 extern _LONG_CALL_ int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num); 393 #define dwc_param_thr_ctl_default 0 394 395 /** Thresholding length for Tx 396 * FIFOs in 32 bit DWORDs 397 */ 398 extern _LONG_CALL_ int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, 399 int32_t val); 400 extern _LONG_CALL_ int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if); 401 #define dwc_param_tx_thr_length_default 64 402 403 /** Thresholding length for Rx 404 * FIFOs in 32 bit DWORDs 405 */ 406 extern _LONG_CALL_ int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, 407 int32_t val); 408 extern _LONG_CALL_ int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if); 409 #define dwc_param_rx_thr_length_default 64 410 411 /** 412 * Specifies whether LPM (Link Power Management) support is enabled 413 */ 414 extern _LONG_CALL_ int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, 415 int32_t val); 416 extern _LONG_CALL_ int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if); 417 #define dwc_param_lpm_enable_default 1 418 419 /** 420 * Specifies whether LPM Errata (Link Power Management) support is enabled 421 */ 422 extern _LONG_CALL_ int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t * core_if, 423 int32_t val); 424 extern _LONG_CALL_ int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t * core_if); 425 #define dwc_param_besl_enable_default 0 426 427 /** 428 * Specifies baseline_besl default value 429 */ 430 extern _LONG_CALL_ int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t * core_if, 431 int32_t val); 432 extern _LONG_CALL_ int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t * core_if); 433 #define dwc_param_baseline_besl_default 0 434 435 /** 436 * Specifies deep_besl default value 437 */ 438 extern _LONG_CALL_ int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t * core_if, 439 int32_t val); 440 extern _LONG_CALL_ int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t * core_if); 441 #define dwc_param_deep_besl_default 15 442 443 /** 444 * Specifies whether PTI enhancement is enabled 445 */ 446 extern _LONG_CALL_ int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, 447 int32_t val); 448 extern _LONG_CALL_ int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if); 449 #define dwc_param_pti_enable_default 0 450 451 /** 452 * Specifies whether MPI enhancement is enabled 453 */ 454 extern _LONG_CALL_ int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, 455 int32_t val); 456 extern _LONG_CALL_ int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if); 457 #define dwc_param_mpi_enable_default 0 458 459 /** 460 * Specifies whether ADP capability is enabled 461 */ 462 extern _LONG_CALL_ int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, 463 int32_t val); 464 extern _LONG_CALL_ int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if); 465 #define dwc_param_adp_enable_default 0 466 467 /** 468 * Specifies whether IC_USB capability is enabled 469 */ 470 471 extern _LONG_CALL_ int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, 472 int32_t val); 473 extern _LONG_CALL_ int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if); 474 #define dwc_param_ic_usb_cap_default 0 475 476 extern _LONG_CALL_ int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, 477 int32_t val); 478 extern _LONG_CALL_ int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if); 479 #define dwc_param_ahb_thr_ratio_default 0 480 481 extern _LONG_CALL_ int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, 482 int32_t val); 483 extern _LONG_CALL_ int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if); 484 #define dwc_param_power_down_default 0 485 486 extern _LONG_CALL_ int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, 487 int32_t val); 488 extern _LONG_CALL_ int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if); 489 #define dwc_param_reload_ctl_default 0 490 491 extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, 492 int32_t val); 493 extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if); 494 #define dwc_param_dev_out_nak_default 0 495 496 extern _LONG_CALL_ int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, 497 int32_t val); 498 extern _LONG_CALL_ int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if); 499 #define dwc_param_cont_on_bna_default 0 500 501 extern _LONG_CALL_ int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, 502 int32_t val); 503 extern _LONG_CALL_ int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if); 504 #define dwc_param_ahb_single_default 0 505 506 extern _LONG_CALL_ int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val); 507 extern _LONG_CALL_ int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if); 508 #define dwc_param_otg_ver_default 0 509 510 /** @} */ 511 512 /** @name Access to registers and bit-fields */ 513 514 /** 515 * Dump core registers and SPRAM 516 */ 517 extern _LONG_CALL_ void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if); 518 extern _LONG_CALL_ void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if); 519 extern _LONG_CALL_ void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if); 520 extern _LONG_CALL_ void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if); 521 522 /** 523 * Get host negotiation status. 524 */ 525 extern _LONG_CALL_ uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if); 526 527 /** 528 * Get srp status 529 */ 530 extern _LONG_CALL_ uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if); 531 532 /** 533 * Set hnpreq bit in the GOTGCTL register. 534 */ 535 extern _LONG_CALL_ void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val); 536 537 /** 538 * Get Content of SNPSID register. 539 */ 540 extern _LONG_CALL_ uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if); 541 542 /** 543 * Get current mode. 544 * Returns 0 if in device mode, and 1 if in host mode. 545 */ 546 extern _LONG_CALL_ uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if); 547 548 /** 549 * Get value of hnpcapable field in the GUSBCFG register 550 */ 551 extern _LONG_CALL_ uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if); 552 /** 553 * Set value of hnpcapable field in the GUSBCFG register 554 */ 555 extern _LONG_CALL_ void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val); 556 557 /** 558 * Get value of srpcapable field in the GUSBCFG register 559 */ 560 extern _LONG_CALL_ uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if); 561 /** 562 * Set value of srpcapable field in the GUSBCFG register 563 */ 564 extern _LONG_CALL_ void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val); 565 566 /** 567 * Get value of devspeed field in the DCFG register 568 */ 569 extern _LONG_CALL_ uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if); 570 /** 571 * Set value of devspeed field in the DCFG register 572 */ 573 extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val); 574 575 /** 576 * Get the value of busconnected field from the HPRT0 register 577 */ 578 extern _LONG_CALL_ uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if); 579 580 /** 581 * Gets the device enumeration Speed. 582 */ 583 extern _LONG_CALL_ uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if); 584 585 /** 586 * Get value of prtpwr field from the HPRT0 register 587 */ 588 extern _LONG_CALL_ uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if); 589 590 /** 591 * Get value of flag indicating core state - hibernated or not 592 */ 593 extern _LONG_CALL_ uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if); 594 595 /** 596 * Set value of prtpwr field from the HPRT0 register 597 */ 598 extern _LONG_CALL_ void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val); 599 600 /** 601 * Get value of prtsusp field from the HPRT0 regsiter 602 */ 603 extern _LONG_CALL_ uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if); 604 /** 605 * Set value of prtpwr field from the HPRT0 register 606 */ 607 extern _LONG_CALL_ void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val); 608 609 /** 610 * Get value of ModeChTimEn field from the HCFG regsiter 611 */ 612 extern _LONG_CALL_ uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if); 613 /** 614 * Set value of ModeChTimEn field from the HCFG regsiter 615 */ 616 extern _LONG_CALL_ void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val); 617 618 /** 619 * Get value of Fram Interval field from the HFIR regsiter 620 */ 621 extern _LONG_CALL_ uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if); 622 /** 623 * Set value of Frame Interval field from the HFIR regsiter 624 */ 625 extern _LONG_CALL_ void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val); 626 627 /** 628 * Set value of prtres field from the HPRT0 register 629 *FIXME Remove? 630 */ 631 extern _LONG_CALL_ void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val); 632 633 /** 634 * Get value of rmtwkupsig bit in DCTL register 635 */ 636 extern _LONG_CALL_ uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if); 637 638 /** 639 * Get value of besl_reject bit in DCTL register 640 */ 641 642 extern _LONG_CALL_ uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t * core_if); 643 644 /** 645 * Set value of besl_reject bit in DCTL register 646 */ 647 648 extern _LONG_CALL_ void dwc_otg_set_beslreject(dwc_otg_core_if_t * core_if, uint32_t val); 649 650 /** 651 * Get value of prt_sleep_sts field from the GLPMCFG register 652 */ 653 extern _LONG_CALL_ uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if); 654 655 /** 656 * Get value of rem_wkup_en field from the GLPMCFG register 657 */ 658 extern _LONG_CALL_ uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if); 659 660 /** 661 * Get value of appl_resp field from the GLPMCFG register 662 */ 663 extern _LONG_CALL_ uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if); 664 /** 665 * Set value of appl_resp field from the GLPMCFG register 666 */ 667 extern _LONG_CALL_ void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val); 668 669 /** 670 * Get value of hsic_connect field from the GLPMCFG register 671 */ 672 extern _LONG_CALL_ uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if); 673 /** 674 * Set value of hsic_connect field from the GLPMCFG register 675 */ 676 extern _LONG_CALL_ void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val); 677 678 /** 679 * Get value of inv_sel_hsic field from the GLPMCFG register. 680 */ 681 extern _LONG_CALL_ uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if); 682 /** 683 * Set value of inv_sel_hsic field from the GLPMFG register. 684 */ 685 extern _LONG_CALL_ void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val); 686 /** 687 * Set value of hird_thresh field from the GLPMFG register. 688 */ 689 extern _LONG_CALL_ void dwc_otg_set_hirdthresh(dwc_otg_core_if_t * core_if, uint32_t val); 690 /** 691 * Get value of hird_thresh field from the GLPMFG register. 692 */ 693 extern _LONG_CALL_ uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t * core_if); 694 695 696 /* 697 * Some functions for accessing registers 698 */ 699 700 /** 701 * GOTGCTL register 702 */ 703 extern _LONG_CALL_ uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if); 704 extern _LONG_CALL_ void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val); 705 706 /** 707 * GUSBCFG register 708 */ 709 extern _LONG_CALL_ uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if); 710 extern _LONG_CALL_ void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val); 711 712 /** 713 * GRXFSIZ register 714 */ 715 extern _LONG_CALL_ uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if); 716 extern _LONG_CALL_ void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); 717 718 /** 719 * GNPTXFSIZ register 720 */ 721 extern _LONG_CALL_ uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if); 722 extern _LONG_CALL_ void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); 723 724 extern _LONG_CALL_ uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if); 725 extern _LONG_CALL_ void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val); 726 727 /** 728 * GGPIO register 729 */ 730 extern _LONG_CALL_ uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if); 731 extern _LONG_CALL_ void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val); 732 733 /** 734 * GUID register 735 */ 736 extern _LONG_CALL_ uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if); 737 extern _LONG_CALL_ void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val); 738 739 /** 740 * HPRT0 register 741 */ 742 extern _LONG_CALL_ uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if); 743 extern _LONG_CALL_ void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val); 744 745 /** 746 * GHPTXFSIZE 747 */ 748 extern _LONG_CALL_ uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if); 749 750 /** @} */ 751 752 #endif /* __DWC_CORE_IF_H__ */ 753