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/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/hal/haas1000/
A Dreg_codec_haas1000.h198 #define CODEC_CODEC_RX_THRESHOLD(n) (((n) & 0xF) << 0) argument
201 #define CODEC_CODEC_TX_THRESHOLD(n) (((n) & 0xF) << 4) argument
204 #define CODEC_CODEC_TX_THRESHOLD_SND(n) (((n) & 0xF) << 8) argument
207 #define CODEC_DSD_RX_THRESHOLD(n) (((n) & 0xF) << 12) argument
210 #define CODEC_DSD_TX_THRESHOLD(n) (((n) & 0x7) << 16) argument
215 #define CODEC_CODEC_RX_OVERFLOW(n) (((n) & 0xFF) << 0) argument
218 #define CODEC_CODEC_RX_UNDERFLOW(n) (((n) & 0xFF) << 8) argument
238 #define CODEC_CODEC_RX_OVERFLOW_MSK(n) (((n) & 0xFF) << 0) argument
241 #define CODEC_CODEC_RX_UNDERFLOW_MSK(n) (((n) & 0xFF) << 8) argument
261 #define CODEC_FIFO_COUNT_CH0(n) (((n) & 0xF) << 0) argument
[all …]
A Dreg_iomux_haas1000.h56 #define IOMUX_GPIO_P00_SEL(n) (((n) & 0xF) << 0) argument
59 #define IOMUX_GPIO_P01_SEL(n) (((n) & 0xF) << 4) argument
62 #define IOMUX_GPIO_P02_SEL(n) (((n) & 0xF) << 8) argument
65 #define IOMUX_GPIO_P03_SEL(n) (((n) & 0xF) << 12) argument
68 #define IOMUX_GPIO_P04_SEL(n) (((n) & 0xF) << 16) argument
71 #define IOMUX_GPIO_P05_SEL(n) (((n) & 0xF) << 20) argument
74 #define IOMUX_GPIO_P06_SEL(n) (((n) & 0xF) << 24) argument
77 #define IOMUX_GPIO_P07_SEL(n) (((n) & 0xF) << 28) argument
82 #define IOMUX_GPIO_P10_SEL(n) (((n) & 0xF) << 0) argument
85 #define IOMUX_GPIO_P11_SEL(n) (((n) & 0xF) << 4) argument
[all …]
A Dreg_cmu_haas1000.h250 #define CMU_CFG_HCLK_MCU_OFF_TIMER(n) (((n) & 0xFF) << 0) argument
258 #define CMU_DEBUG_REG_SEL(n) (((n) & 0x7) << 13) argument
276 #define CMU_CFG_DIV_SDMMC(n) (((n) & 0xF) << 0) argument
282 #define CMU_SEL_32K_TIMER(n) (((n) & 0x7) << 7) argument
286 #define CMU_SEL_TIMER_FAST(n) (((n) & 0x7) << 11) argument
289 #define CMU_CFG_CLK_OUT(n) (((n) & 0xF) << 14) argument
352 #define CMU_ROM_EMA(n) (((n) & 0x7) << 0) argument
356 #define CMU_ROM_PGEN(n) (((n) & 0x3) << 4) argument
359 #define CMU_RAM_EMA(n) (((n) & 0x7) << 6) argument
362 #define CMU_RAM_EMAW(n) (((n) & 0x3) << 9) argument
[all …]
A Dreg_aoncmu_haas1000.h53 #define AON_CMU_CHIP_ID(n) (((n) & 0xFFFF) << 0) argument
56 #define AON_CMU_REVISION_ID(n) (((n) & 0xFFFF) << 16) argument
175 #define AON_CMU_CFG_DIV_BTSYS(n) (((n) & 0x3) << 1) argument
181 #define AON_CMU_CFG_DIV_USB(n) (((n) & 0x7) << 6) argument
185 #define AON_CMU_CFG_DIV_PER(n) (((n) & 0x3) << 10) argument
204 #define AON_CMU_SEL_CLK_OUT(n) (((n) & 0x7) << 1) argument
207 #define AON_CMU_CFG_CLK_OUT(n) (((n) & 0x1F) << 4) argument
210 #define AON_CMU_CFG_DIV_DCDC(n) (((n) & 0xF) << 9) argument
216 #define AON_CMU_CLK_DCDC_DRV(n) (((n) & 0x3) << 16) argument
264 #define AON_CMU_CFG_DIV_FLS(n) (((n) & 0x7) << 4) argument
[all …]
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/hal/
A Dreg_psramuhs_mc.h105 #define PSRAM_UHS_MC_CHIP_CA_PATTERN(n) (((n) & 0x7) << 4) argument
108 #define PSRAM_UHS_MC_CHIP_MEM_SIZE(n) (((n) & 0x3) << 7) argument
113 #define PSRAM_UHS_MC_MGR_CMD(n) (((n) & 0xFF) << 0) argument
123 #define PSRAM_UHS_MC_MGR_LEN(n) (((n) & 0xFF) << 0) argument
155 #define PSRAM_UHS_MC_RES_7_4_REG24(n) (((n) & 0xF) << 4) argument
158 #define PSRAM_UHS_MC_PD_MR(n) (((n) & 0xFF) << 8) argument
163 #define PSRAM_UHS_MC_WRITE_LATENCY(n) (((n) & 0xFF) << 0) argument
173 #define PSRAM_UHS_MC_MEMORY_WIDTH(n) (((n) & 0x3) << 0) argument
178 #define PSRAM_UHS_MC_BURST_LENGTH(n) (((n) & 0x7) << 0) argument
182 #define PSRAM_UHS_MC_PAGE_BOUNDARY(n) (((n) & 0x3) << 4) argument
[all …]
A Dreg_psram_mc_v2.h99 #define PSRAM_ULP_MC_CHIP_CA_PATTERN(n) (((n) & 0x7) << 3) argument
104 #define PSRAM_ULP_MC_MGR_CMD(n) (((n) & 0xFF) << 0) argument
114 #define PSRAM_ULP_MC_MGR_LEN(n) (((n) & 0xFF) << 0) argument
119 #define PSRAM_ULP_MC_MGR_WSTRB(n) (((n) & 0xFF) << 0) argument
146 #define PSRAM_ULP_MC_RES_7_4_REG24(n) (((n) & 0xF) << 4) argument
149 #define PSRAM_ULP_MC_PD_MR(n) (((n) & 0xFF) << 8) argument
157 #define PSRAM_ULP_MC_WRITE_LATENCY(n) (((n) & 0xFF) << 0) argument
167 #define PSRAM_ULP_MC_MEMORY_WIDTH(n) (((n) & 0x3) << 0) argument
172 #define PSRAM_ULP_MC_BURST_LENGTH(n) (((n) & 0x7) << 0) argument
176 #define PSRAM_ULP_MC_PAGE_BOUNDARY(n) (((n) & 0x3) << 4) argument
[all …]
A Dhal_location.h11 #define HAL_SEC_DEF_A(s, d, n) __attribute__((section(#s #d #n))) n argument
73 #define BOOT_TEXT_SRAM_DEF(n) n
79 #define BOOT_TEXT_FLASH_DEF(n) n
82 #define BOOT_RODATA_DEF(n) n
84 #define BOOT_DATA_DEF(n) n
86 #define BOOT_BSS_DEF(n) n
89 #define SRAM_TEXT_DEF(n) n
91 #define SRAM_DATA_DEF(n) n
93 #define SRAM_STACK_DEF(n) n
95 #define SRAM_BSS_DEF(n) n
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A Dreg_xdma.h75 #define XDMA_CONFIG_CHLNUM(n) ((((n) & 0x1F) << 0)) // Chann… argument
82 #define XDMA_CONFIG_DESCRIPTOR_STOP(n) ((((n) & 0x1) << 0)) // Stop argument
86 #define XDMA_CONFIG_SRCADDR2(n) ((((n) & 0x1) << 2)) // argument
87 #define XDMA_CONFIG_SRCADDR0(n) ((((n) & 0x3) << 0)) // argument
91 #define XDMA_CONFIG_TRGADDR2(n) ((((n) & 0x1) << 2)) // argument
92 #define XDMA_CONFIG_TRGADDR0(n) ((((n) & 0x3) << 0)) // argument
100 #define XDMA_CONTROL_ADDRMODE(n) ((((n) & 0x01) << 23)) // transfer width argument
103 #define XDMA_CONTROL_MAXBSIZE(n) ((((n) & 0x07) << 16)) // MAX burst size argument
104 #define XDMA_CONTROL_WIDTH(n) ((((n) & 0x03) << 14)) // transfer width argument
107 #define XDMA_CONTROL_TRANSFERSIZE(n) ((((n) & 0x1FFF) << 0)) // Transfer size argument
[all …]
A Dreg_norflaship_v2.h88 #define REG_000_ADDR(n) BITFIELD_VAL(REG_000_ADDR, n) argument
91 #define REG_000_CMD(n) BITFIELD_VAL(REG_000_CMD, n) argument
111 #define REG_004_RES26(n) BITFIELD_VAL(REG_004_RES26, n) argument
121 #define REG_004_RES1(n) BITFIELD_VAL(REG_004_RES1, n) argument
127 #define REG_008_TXDATA(n) BITFIELD_VAL(REG_008_TXDATA, n) argument
132 #define REG_00C_RES(n) BITFIELD_VAL(REG_00C_RES, n) argument
152 #define REG_014_RES29(n) BITFIELD_VAL(REG_014_RES29, n) argument
180 #define REG_018_RES(n) BITFIELD_VAL(REG_018_RES, n) argument
230 #define REG_02C_RES(n) BITFIELD_VAL(REG_02C_RES, n) argument
236 #define REG_030_RES(n) BITFIELD_VAL(REG_030_RES, n) argument
[all …]
A Dreg_usb.h210 #define USBC_HBSTLEN(n) (((n)&15)<<1) argument
224 #define USBC_TOUTCAL(n) (((n)&7)<<0) argument
248 #define USBC_USBTRDTIM(n) (((n)&15)<<10) argument
301 #define USBC_TXFNUM(n) (((n)&31)<<6) argument
490 #define USBC_EPNUM(n) (((n)&15)<<0) argument
496 #define USBC_DPID(n) (((n)&3)<<15) argument
589 #define USBC_OTGMODE(n) (((n)&7)<<0) argument
592 #define USBC_OTGARCH(n) (((n)&3)<<3) argument
598 #define USBC_HSPHYTYPE(n) (((n)&3)<<6) argument
601 #define USBC_FSPHYTYPE(n) (((n)&3)<<8) argument
[all …]
A Dreg_psram_phy_v2.h39 #define PSRAM_ULP_PHY_MEMORY_WIDTH(n) (((n) & 0x3) << 2) argument
42 #define PSRAM_ULP_PHY_FRE_RATIO(n) (((n) & 0x3) << 4) argument
47 #define PSRAM_ULP_PHY_CTRL_DELAY(n) (((n) & 0x3) << 0) argument
56 #define PSRAM_ULP_PHY_T_WPST(n) (((n) & 0x7) << 0) argument
61 #define PSRAM_ULP_PHY_RESERVED(n) (((n) & 0x3F) << 0) argument
75 #define PSRAM_ULP_PHY_PHY_FSM_STATE(n) (((n) & 0xF) << 1) argument
82 #define PSRAM_ULP_PHY_REG_LDO_IEN1(n) (((n) & 0xF) << 2) argument
85 #define PSRAM_ULP_PHY_REG_LDO_IEN2(n) (((n) & 0xF) << 6) argument
94 #define PSRAM_ULP_PHY_REG_PSRAM_SWRC(n) (((n) & 0x3) << 1) argument
97 #define PSRAM_ULP_PHY_REG_PSRAM_TXDRV(n) (((n) & 0x7) << 3) argument
[all …]
A Dreg_pwm.h36 #define PWM_PHASE01_0(n) (((n) & 0xFFFF) << 0) argument
39 #define PWM_PHASE01_1(n) (((n) & 0xFFFF) << 16) argument
43 #define PWM_PHASE23_2(n) (((n) & 0xFFFF) << 0) argument
46 #define PWM_PHASE23_3(n) (((n) & 0xFFFF) << 16) argument
50 #define PWM_LOAD01_0(n) (((n) & 0xFFFF) << 0) argument
53 #define PWM_LOAD01_1(n) (((n) & 0xFFFF) << 16) argument
57 #define PWM_LOAD23_2(n) (((n) & 0xFFFF) << 0) argument
60 #define PWM_LOAD23_3(n) (((n) & 0xFFFF) << 16) argument
64 #define PWM_TOGGLE01_0(n) (((n) & 0xFFFF) << 0) argument
67 #define PWM_TOGGLE01_1(n) (((n) & 0xFFFF) << 16) argument
[all …]
A Dreg_sec_eng.h165 #define ADEC_CTRL_RST_15_0(n) BITFIELD_VAL(ADEC_CTRL_RST_15_0, n) argument
200 #define ACB_CTRL_RSVD_31_11(n) BITFIELD_VAL(ACB_CTRL_RSVD_31_11, n) argument
216 #define AES_CFG_RSVD_31_17(n) BITFIELD_VAL(AES_CFG_RSVD_31_17, n) argument
221 #define AES_CFG_MODULAR(n) BITFIELD_VAL(AES_CFG_MODULAR, n) argument
226 #define AES_CFG_MODE(n) BITFIELD_VAL(AES_CFG_MODE, n) argument
229 #define AES_CFG_KEYLEN(n) BITFIELD_VAL(AES_CFG_KEYLEN, n) argument
235 #define AES_CTRL_RSVD_31_3(n) BITFIELD_VAL(AES_CTRL_RSVD_31_3, n) argument
243 #define AES_CMD_RSVD_31_1(n) BITFIELD_VAL(AES_CMD_RSVD_31_1, n) argument
252 #define AES_STATUS_STATE(n) BITFIELD_VAL(AES_STATUS_STATE, n) argument
320 #define HMAC_KEY_LEN_LEN(n) BITFIELD_VAL(HMAC_KEY_LEN_LEN, n) argument
[all …]
A Dreg_dma.h59 #define DMA_CONTROL_TRANSFERSIZE(n) ((((n) & 0xFFF) << 0)) // Transfer size argument
62 #define DMA_CONTROL_SBSIZE(n) ((((n) & 0x07) << 12)) // Source burst size argument
63 #define DMA_CONTROL_DBSIZE(n) ((((n) & 0x07) << 15)) // Destination burst size argument
64 #define DMA_CONTROL_SWIDTH(n) ((((n) & 0x07) << 18)) // Source transfer width argument
67 #define DMA_CONTROL_DWIDTH(n) ((((n) & 0x07) << 21)) // Destination transfer width argument
80 #define DMA_CONFIG_SRCPERIPH(n) ((((n) & 0x1F) << 1)) // Source peripheral argument
81 #define DMA_CONFIG_DSTPERIPH(n) ((((n) & 0x1F) << 6)) // Destination peripheral argument
90 #define DMA_STAT_CHAN(n) ((1 << (n)) & 0xFF) argument
99 #define DMA_DMACONFIG_TC_IRQ_EN(n) (((n) & 0xFF) << 4) argument
107 #define DMA_2D_MODIFY(n) BITFIELD_VAL(DMA_2D_MODIFY, n) argument
[all …]
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/drivers/ana/haas1000/
A Dreg_usbphy_haas1000.h12 #define REVID(n) BITFIELD_VAL(REVID, n) argument
15 #define CHIPID(n) BITFIELD_VAL(CHIPID, n) argument
48 #define CFG_EBUF_THRD(n) BITFIELD_VAL(CFG_EBUF_THRD, n) argument
53 #define CFG_TARGET_TAIL(n) BITFIELD_VAL(CFG_TARGET_TAIL, n) argument
56 #define CFG_TXPATTERN(n) BITFIELD_VAL(CFG_TXPATTERN, n) argument
68 #define CFG_TP_SEL(n) BITFIELD_VAL(CFG_TP_SEL, n) argument
86 #define CFG_FS_DRV_SEL(n) BITFIELD_VAL(CFG_FS_DRV_SEL, n) argument
127 #define CFG_I_RCV_REG(n) BITFIELD_VAL(CFG_I_RCV_REG, n) argument
430 #define REV_REG30(n) BITFIELD_VAL(REV_REG30, n) argument
435 #define REV_REG31(n) BITFIELD_VAL(REV_REG31, n) argument
[all …]
A Dreg_psramuhsphy_haas1000.h35 #define REVID(n) BITFIELD_VAL(REVID, n) argument
48 #define REG_LDO_VTUNE(n) BITFIELD_VAL(REG_LDO_VTUNE, n) argument
51 #define REG_VREF_VTUNE(n) BITFIELD_VAL(REG_VREF_VTUNE, n) argument
54 #define REG_LDO_IEN1(n) BITFIELD_VAL(REG_LDO_IEN1, n) argument
57 #define REG_LDO_IEN2(n) BITFIELD_VAL(REG_LDO_IEN2, n) argument
60 #define REG_PSRAM_SWRC(n) BITFIELD_VAL(REG_PSRAM_SWRC, n) argument
65 #define REG_PSRAM_ODT(n) BITFIELD_VAL(REG_PSRAM_ODT, n) argument
68 #define REG_DLL_SWRC(n) BITFIELD_VAL(REG_DLL_SWRC, n) argument
71 #define REG_DLL_RANGE(n) BITFIELD_VAL(REG_DLL_RANGE, n) argument
77 #define DLL_DLY_IN(n) BITFIELD_VAL(DLL_DLY_IN, n) argument
[all …]
A Dreg_ddrpll_haas1000.h37 #define REG_DDRPLL_VCO_CAL_VT(n) BITFIELD_VAL(REG_DDRPLL_VCO_CAL_VT, n) argument
45 #define REG_DDRPLL_PATH_EN(n) BITFIELD_VAL(REG_DDRPLL_PATH_EN, n) argument
48 #define REG_DDRPLL_PDIV_PSRAM(n) BITFIELD_VAL(REG_DDRPLL_PDIV_PSRAM, n) argument
56 #define REG_DDRPLL_BUF_VRES(n) BITFIELD_VAL(REG_DDRPLL_BUF_VRES, n) argument
59 #define REG_DDRPLL_BW_SEL(n) BITFIELD_VAL(REG_DDRPLL_BW_SEL, n) argument
67 #define REG_DDRPLL_CP_VRES(n) BITFIELD_VAL(REG_DDRPLL_CP_VRES, n) argument
76 #define REG_DDRPLL_FBRES(n) BITFIELD_VAL(REG_DDRPLL_FBRES, n) argument
79 #define REG_DDRPLL_ICP(n) BITFIELD_VAL(REG_DDRPLL_ICP, n) argument
84 #define REG_DDRPLL_IOFST(n) BITFIELD_VAL(REG_DDRPLL_IOFST, n) argument
110 #define RESERVED_1(n) BITFIELD_VAL(RESERVED_1, n) argument
[all …]
A Dreg_dsppll_haas1000.h37 #define REG_A7PLL_VCO_CAL_VT(n) BITFIELD_VAL(REG_A7PLL_VCO_CAL_VT, n) argument
47 #define REG_A7PLL_BUF_VRES(n) BITFIELD_VAL(REG_A7PLL_BUF_VRES, n) argument
50 #define REG_A7PLL_BW_SEL(n) BITFIELD_VAL(REG_A7PLL_BW_SEL, n) argument
56 #define REG_A7PLL_POSTDIV(n) BITFIELD_VAL(REG_A7PLL_POSTDIV, n) argument
61 #define REG_A7PLL_CP_VRES(n) BITFIELD_VAL(REG_A7PLL_CP_VRES, n) argument
70 #define REG_A7PLL_FBRES(n) BITFIELD_VAL(REG_A7PLL_FBRES, n) argument
73 #define REG_A7PLL_ICP(n) BITFIELD_VAL(REG_A7PLL_ICP, n) argument
78 #define REG_A7PLL_IOFST(n) BITFIELD_VAL(REG_A7PLL_IOFST, n) argument
104 #define RESERVED_2(n) BITFIELD_VAL(RESERVED_2, n) argument
130 #define REG_A7PLL_MULT(n) BITFIELD_VAL(REG_A7PLL_MULT, n) argument
[all …]
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/tensorflow/lite/experimental/microfrontend/lib/
A Dbits.h26 if (n >> 16) zeroes -= 16, n >>= 16; in CountLeadingZeros32Slow()
27 if (n >> 8) zeroes -= 8, n >>= 8; in CountLeadingZeros32Slow()
28 if (n >> 4) zeroes -= 4, n >>= 4; in CountLeadingZeros32Slow()
42 if (n == 0) { in CountLeadingZeros32()
45 return __builtin_clz(n); in CountLeadingZeros32()
57 if (n >> 32) zeroes -= 32, n >>= 32; in CountLeadingZeros64Slow()
58 if (n >> 16) zeroes -= 16, n >>= 16; in CountLeadingZeros64Slow()
59 if (n >> 8) zeroes -= 8, n >>= 8; in CountLeadingZeros64Slow()
60 if (n >> 4) zeroes -= 4, n >>= 4; in CountLeadingZeros64Slow()
75 if ((n >> 32) && _BitScanReverse(&result, n >> 32)) { in CountLeadingZeros64()
[all …]
/AliOS-Things-master/documentation/manual/
A Dcomponent.md30 @subpage a2sa \n
35 @subpage cli \n
42 @subpage http \n
43 @subpage init \n
45 @subpage kv \n
49 @subpage lwip \n
52 @subpage mqtt \n
54 @subpage oss \n
55 @subpage ota \n
59 @subpage SDL2 \n
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/AliOS-Things-master/solutions/tflite_micro_speech_demo/micro_speech/train/
A Dtrain_micro_speech_model.ipynb17 "\n",
19 "\n"
30 "\n",
32 "\n",
49 "\n",
58 "\n",
62 "\n",
99 "\n",
104 "\n",
110 "\n",
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/AliOS-Things-master/components/amp/engine/quickjs_engine/quickjs/tests/
A Dmicrobench.js55 n *= 10;
81 for (i = 0, n = arguments.length; i < n; i++) {
164 n = n * [ 2, 2.5, 2 ][i % 3];
179 return n;
187 return n;
241 return n;
797 arr[n >> 2] = def[n];
873 log_one("sort_" + f.name, n, ti, n * 100);
889 return n;
899 return n;
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/AliOS-Things-master/components/amp/engine/quickjs_engine/quickjs/examples/
A Dpi_bigint.js10 k_max = 0n;
11 while ((a >> (2n ** k_max)) != 0n) {
14 k = 0n;
16 for(i = k_max - 1n; i >= 0n; i--) {
18 if (a1 != 0n) {
29 return floor_log2(a - 1n) + 1n;
36 if (a == 0n)
39 u = 1n << ((l + 1n) / 2n);
62 G = (2n * b - 1n) * (6n * b - 1n) * (6n * b - 5n);
83 n = BigInt(Math.ceil(Number(prec) / CHUD_BITS_PER_TERM)) + 10n;
[all …]
/AliOS-Things-master/components/lwip/lwip2.0.0/include/lwip/
A Dnetifapi.h96 #define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) argument
98 #define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) argument
100 #define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) argument
102 #define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) argument
114 #define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) argument
116 #define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) argument
118 #define netifapi_dhcp_inform(n) netifapi_netif_common(n, dhcp_inform, NULL) argument
120 #define netifapi_dhcp_renew(n) netifapi_netif_common(n, NULL, dhcp_renew) argument
122 #define netifapi_dhcp_release(n) netifapi_netif_common(n, NULL, dhcp_release) argument
130 #define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) argument
[all …]
/AliOS-Things-master/components/amp/libjs/
A Dinit.js1 …n,e=t.Promise,o=e&&"resolve"in e&&"reject"in e&&"all"in e&&"race"in e&&(new e(function(t){n=t}),"f… argument

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