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Searched refs:op_addr (Results 1 – 19 of 19) sorted by relevance

/AliOS-Things-master/components/csi/csi1/include/core/
A Dcore_rv32_old.h973 op_addr += linesize; in csi_dcache_invalid_range()
975 op_addr += linesize; in csi_dcache_invalid_range()
977 op_addr += linesize; in csi_dcache_invalid_range()
979 op_addr += linesize; in csi_dcache_invalid_range()
981 op_addr += linesize; in csi_dcache_invalid_range()
983 op_addr += linesize; in csi_dcache_invalid_range()
985 op_addr += linesize; in csi_dcache_invalid_range()
987 op_addr += linesize; in csi_dcache_invalid_range()
994 op_addr += linesize; in csi_dcache_invalid_range()
1018 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_802.h1138 op_addr += linesize; in csi_dcache_invalid_range()
1140 op_addr += linesize; in csi_dcache_invalid_range()
1142 op_addr += linesize; in csi_dcache_invalid_range()
1144 op_addr += linesize; in csi_dcache_invalid_range()
1146 op_addr += linesize; in csi_dcache_invalid_range()
1148 op_addr += linesize; in csi_dcache_invalid_range()
1150 op_addr += linesize; in csi_dcache_invalid_range()
1152 op_addr += linesize; in csi_dcache_invalid_range()
1159 op_addr += linesize; in csi_dcache_invalid_range()
1183 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_805.h1150 op_addr += linesize; in csi_dcache_invalid_range()
1152 op_addr += linesize; in csi_dcache_invalid_range()
1154 op_addr += linesize; in csi_dcache_invalid_range()
1156 op_addr += linesize; in csi_dcache_invalid_range()
1158 op_addr += linesize; in csi_dcache_invalid_range()
1160 op_addr += linesize; in csi_dcache_invalid_range()
1162 op_addr += linesize; in csi_dcache_invalid_range()
1164 op_addr += linesize; in csi_dcache_invalid_range()
1171 op_addr += linesize; in csi_dcache_invalid_range()
1195 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_803.h1154 op_addr += linesize; in csi_dcache_invalid_range()
1156 op_addr += linesize; in csi_dcache_invalid_range()
1158 op_addr += linesize; in csi_dcache_invalid_range()
1160 op_addr += linesize; in csi_dcache_invalid_range()
1162 op_addr += linesize; in csi_dcache_invalid_range()
1164 op_addr += linesize; in csi_dcache_invalid_range()
1166 op_addr += linesize; in csi_dcache_invalid_range()
1168 op_addr += linesize; in csi_dcache_invalid_range()
1175 op_addr += linesize; in csi_dcache_invalid_range()
1199 op_addr += linesize; in csi_dcache_clean_range()
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A Dcore_804.h1155 op_addr += linesize; in csi_dcache_invalid_range()
1157 op_addr += linesize; in csi_dcache_invalid_range()
1159 op_addr += linesize; in csi_dcache_invalid_range()
1161 op_addr += linesize; in csi_dcache_invalid_range()
1163 op_addr += linesize; in csi_dcache_invalid_range()
1165 op_addr += linesize; in csi_dcache_invalid_range()
1167 op_addr += linesize; in csi_dcache_invalid_range()
1169 op_addr += linesize; in csi_dcache_invalid_range()
1176 op_addr += linesize; in csi_dcache_invalid_range()
1200 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_rv32.h909 uint32_t op_addr = (uint32_t)addr; in csi_dcache_invalid_range() local
915 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
916 op_addr += linesize; in csi_dcache_invalid_range()
936 uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
942 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
943 op_addr += linesize; in csi_dcache_clean_range()
963 uint32_t op_addr = (uint32_t) addr; in csi_dcache_clean_invalid_range() local
969 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
970 op_addr += linesize; in csi_dcache_clean_invalid_range()
/AliOS-Things-master/components/csi/csi2/include/core/
A Dcore_rv32_old.h973 op_addr += linesize; in csi_dcache_invalid_range()
975 op_addr += linesize; in csi_dcache_invalid_range()
977 op_addr += linesize; in csi_dcache_invalid_range()
979 op_addr += linesize; in csi_dcache_invalid_range()
981 op_addr += linesize; in csi_dcache_invalid_range()
983 op_addr += linesize; in csi_dcache_invalid_range()
985 op_addr += linesize; in csi_dcache_invalid_range()
987 op_addr += linesize; in csi_dcache_invalid_range()
994 op_addr += linesize; in csi_dcache_invalid_range()
1018 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_802.h1152 op_addr += linesize; in csi_dcache_invalid_range()
1154 op_addr += linesize; in csi_dcache_invalid_range()
1156 op_addr += linesize; in csi_dcache_invalid_range()
1158 op_addr += linesize; in csi_dcache_invalid_range()
1160 op_addr += linesize; in csi_dcache_invalid_range()
1162 op_addr += linesize; in csi_dcache_invalid_range()
1164 op_addr += linesize; in csi_dcache_invalid_range()
1166 op_addr += linesize; in csi_dcache_invalid_range()
1173 op_addr += linesize; in csi_dcache_invalid_range()
1197 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_803.h1171 op_addr += linesize; in csi_dcache_invalid_range()
1173 op_addr += linesize; in csi_dcache_invalid_range()
1175 op_addr += linesize; in csi_dcache_invalid_range()
1177 op_addr += linesize; in csi_dcache_invalid_range()
1179 op_addr += linesize; in csi_dcache_invalid_range()
1181 op_addr += linesize; in csi_dcache_invalid_range()
1183 op_addr += linesize; in csi_dcache_invalid_range()
1185 op_addr += linesize; in csi_dcache_invalid_range()
1192 op_addr += linesize; in csi_dcache_invalid_range()
1216 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_804.h1175 op_addr += linesize; in csi_dcache_invalid_range()
1177 op_addr += linesize; in csi_dcache_invalid_range()
1179 op_addr += linesize; in csi_dcache_invalid_range()
1181 op_addr += linesize; in csi_dcache_invalid_range()
1183 op_addr += linesize; in csi_dcache_invalid_range()
1185 op_addr += linesize; in csi_dcache_invalid_range()
1187 op_addr += linesize; in csi_dcache_invalid_range()
1189 op_addr += linesize; in csi_dcache_invalid_range()
1196 op_addr += linesize; in csi_dcache_invalid_range()
1220 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_805.h1167 op_addr += linesize; in csi_dcache_invalid_range()
1169 op_addr += linesize; in csi_dcache_invalid_range()
1171 op_addr += linesize; in csi_dcache_invalid_range()
1173 op_addr += linesize; in csi_dcache_invalid_range()
1175 op_addr += linesize; in csi_dcache_invalid_range()
1177 op_addr += linesize; in csi_dcache_invalid_range()
1179 op_addr += linesize; in csi_dcache_invalid_range()
1181 op_addr += linesize; in csi_dcache_invalid_range()
1188 op_addr += linesize; in csi_dcache_invalid_range()
1212 op_addr += linesize; in csi_dcache_clean_range()
[all …]
A Dcore_rv32.h948 uint32_t op_addr = (uint32_t)addr; in csi_dcache_invalid_range() local
954 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
955 op_addr += linesize; in csi_dcache_invalid_range()
975 uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
981 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
982 op_addr += linesize; in csi_dcache_clean_range()
1002 uint32_t op_addr = (uint32_t) addr; in csi_dcache_clean_invalid_range() local
1008 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
1009 op_addr += linesize; in csi_dcache_clean_invalid_range()
/AliOS-Things-master/components/csi/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/tensorflow/lite/micro/tools/make/downloads/cmsis/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/third_party/cmsis/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/cmsis/
A Dcore_cache.h305 uint32_t op_addr = (uint32_t)addr; in SCB_InvalidateDCache_by_Addr() local
311 SCB->DCIMVAC = op_addr; in SCB_InvalidateDCache_by_Addr()
312 op_addr += (uint32_t)linesize; in SCB_InvalidateDCache_by_Addr()
332 uint32_t op_addr = (uint32_t) addr; in SCB_CleanDCache_by_Addr() local
338 SCB->DCCMVAC = op_addr; in SCB_CleanDCache_by_Addr()
339 op_addr += (uint32_t)linesize; in SCB_CleanDCache_by_Addr()
359 uint32_t op_addr = (uint32_t) addr; in SCB_CleanInvalidateDCache_by_Addr() local
365 SCB->DCCIMVAC = op_addr; in SCB_CleanInvalidateDCache_by_Addr()
366 op_addr += (uint32_t)linesize; in SCB_CleanInvalidateDCache_by_Addr()
/AliOS-Things-master/hardware/board/c906/csi_core/include/
A Dcore_rv64.h900 uint64_t op_addr = (uint64_t)addr; in csi_dcache_invalid_range() local
906 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
907 op_addr += linesize; in csi_dcache_invalid_range()
928 uint64_t op_addr = (uint64_t) addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
934 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
935 op_addr += linesize; in csi_dcache_clean_range()
956 uint64_t op_addr = (uint64_t) addr; in csi_dcache_clean_invalid_range() local
962 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
963 op_addr += linesize; in csi_dcache_clean_invalid_range()
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/cmsis/inc/
A Dcore_cm7.h2483 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
2488 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
2489 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2513 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
2518 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
2519 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2543 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
2548 …SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanInvalidateDCache_by_Addr()
2549 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()
/AliOS-Things-master/components/py_engine/engine/lib/cmsis/inc/
A Dcore_cm7.h2483 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
2488 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
2489 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
2513 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
2518 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
2519 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
2543 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
2548 …SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanInvalidateDCache_by_Addr()
2549 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanInvalidateDCache_by_Addr()

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