1 /* 2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited 3 */ 4 5 6 /****************************************************************************** 7 * @file dw_gpio.h 8 * @brief header file for GPIO Driver 9 * @version V1.0 10 * @date 02. June 2017 11 ******************************************************************************/ 12 #ifndef _DW_GPIO_H_ 13 #define _DW_GPIO_H_ 14 15 #include "drv_gpio.h" 16 #include "soc.h" 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 23 typedef struct { 24 __IOM uint32_t SWPORT_DR; /* Offset: 0x000 (W/R) PortA data register */ 25 __IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (W/R) PortA data direction register */ 26 __IOM uint32_t PORT_CTL; /* Offset: 0x008 (W/R) PortA source register */ 27 28 } dw_gpio_reg_t; 29 30 typedef struct { 31 __IOM uint32_t INTEN; /* Offset: 0x000 (W/R) Interrupt enable register */ 32 __IOM uint32_t INTMASK; /* Offset: 0x004 (W/R) Interrupt mask register */ 33 __IOM uint32_t INTTYPE_LEVEL; /* Offset: 0x008 (W/R) Interrupt level register */ 34 __IOM uint32_t INT_POLARITY; /* Offset: 0x00c (W/R) Interrupt polarity register */ 35 __IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */ 36 __IM uint32_t RAWINTSTATUS; /* Offset: 0x014 (W/R) Raw interrupt status of Port */ 37 __IOM uint32_t revreg1; /* Offset: 0x018 (W/R) Reserve register */ 38 __OM uint32_t PORTA_EOI; /* Offset: 0x01c (W/R) Port clear interrupt register */ 39 __IM uint32_t EXT_PORTA; /* Offset: 0x020 (W/R) PortA external port register */ 40 __IM uint32_t EXT_PORTB; /* Offset: 0x024 (W/R) PortB external port register */ 41 __IOM uint32_t revreg2[2]; /* Offset: 0x028 (W/R) Reserve register */ 42 __IOM uint32_t LS_SYNC; /* Offset: 0x030 (W/R) Level-sensitive synchronization enable register */ 43 44 } dw_gpio_control_reg_t; 45 46 #ifdef __cplusplus 47 } 48 #endif 49 50 #endif 51 52