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/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Drtl8721d_usi.h85 #define USI_TX_FIFO_DATA ((u32)0x000000FF) /*BIT[7:0], TX DATA*/
119 #define USI_RX_FIFO_DATA ((u32)0x000000FF) /*BIT[7:0], TX DATA*/
661 #define USI_I2C_ANA_DATA_DEG_RL ((u32)0x000FFFFF) /*BIT[19:0]*/
669 #define USI_I2C_ANA_DATA_DEG_RM ((u32)0x000FFFFF) /*BIT[19:0]*/
677 #define USI_I2C_ANA_CLK_DEG_RL ((u32)0x000FFFFF) /*BIT[19:0]*/
685 #define USI_I2C_ANA_CLK_DEG_RM ((u32)0x000FFFFF) /*BIT[19:0]*/
693 #define USI_I2C_ANA_DATA_DEG_CL ((u32)0x000FFFFF) /*BIT[19:0]*/
701 #define USI_I2C_ANA_DATA_DEG_CM ((u32)0x0000001F) /*BIT[4:0]*/
717 #define USI_I2C_ANA_CLK_DEG_CM ((u32)0x0000001F) /*BIT[4:0]*/
737 u32 Tx_HandshakeInterface;
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A Drtl8721d_sgpio.h714 void SGPIO_RXMR0Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0Val, u32 SGPIO_RXMR0Ctl);
715 void SGPIO_RXMR1Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR1Val, u32 SGPIO_RXMR1Ctl);
717 void SGPIO_RXMRxTXConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0TXCtl, u32 SGPIO_RXMR1TXCtl, u32 SGP…
724 void SGPIO_MULMR0MulConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0Val0, u32 SGPIO_MULMR0Val1, u32 S…
725 void SGPIO_MULMR0RXConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0Val0, u32 SGPIO_MULMR0Val1, u32 SG…
726 …_MULMRxGP0ValConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0GP0, u32 SGPIO_MULMR1GP0, u32 SGPIO_MUL…
727 …_MULMRxGP1ValConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0GP1, u32 SGPIO_MULMR1GP1, u32 SGPIO_MUL…
728 …ULMRxTXCtlConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0TXCtl, u32 SGPIO_MULMR1TXCtl, u32 SGPIO_MU…
739 void SGPIO_Cap_CompConfig(SGPIO_TypeDef *SGPIOx, u32 CapComp_Val, u32 CapComp_Mode);
742 void SGPIO_INTConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_IT, u32 NewState);
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A Drtl8721d_lcdc.h494 #define LCDC_MCU_IO_MODE ((u32)0x00000800)
628 #define LCDC_RGB_DE_MODE ((u32)0x00000000)
629 #define LCDC_RGB_HV_MODE ((u32)0x02000000)
700 #define LCDC_LED_IF ((u32)0x000f0000)
798 #define LCDC_IT_LINE ((u32)0x00000008)
799 #define LCDC_IT_FRDN ((u32)0x00000004)
800 #define LCDC_IT_DMAUNDFW ((u32)0x00000001)
852 _LONG_CALL_ void LCDC_RGBGetSyncStatus(LCDC_TypeDef* LCDCx, u32 * pHSStatus, u32 * pVSStatus);
872 _LONG_CALL_ void LCDC_DMAUnderFlowConfig(LCDC_TypeDef* LCDCx, u32 DmaUnFlwMode, u32 ErrorData);
882 _LONG_CALL_ void LCDC_INTConfig(LCDC_TypeDef* LCDCx, u32 LCDC_IT, u32 NewState);
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A Drtl8721d_qdec.h148 #define QD_SYS_CLK_32K ((u32)32768)
203 #define QD_IDX_NORMAL (((u32)0x00000001 << 31) | ((u32)0x00000000 << 5))
204 #define QD_IDX_INVERSE (((u32)0x00000001 << 31) | ((u32)0x00000001 << 5))
274 u32 QDEC_GetRC(QDEC_TypeDef *QDec);
276 u32 QDEC_GetDir(QDEC_TypeDef *QDec);
277 u32 QDEC_GetPC(QDEC_TypeDef *QDec);
279 void QDEC_SetRstMod(QDEC_TypeDef *QDec, u32 mode, u32 phase);
286 u32 QDEC_GetVT(QDEC_TypeDef *QDec);
287 u32 QDEC_GetVC(QDEC_TypeDef *QDec);
290 void QDEC_INTConfig(QDEC_TypeDef *QDec, u32 INT, u32 newState);
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A Drtl8721d_crypto.h117 u32 zero:1; /*Offset 0, Bit[13], 0/1 */
125 u32 w;
152 u32 w;
221 u32 cipher_type; /*cipher type */
228 u32 auth_type; /*auth type */
238 u32 lenAuthKey; /*Auth key length */
240 u32 digestlen; /*digest */
292 #define AUTH_TYPE_NO_AUTH ((u32)-1)
330 #define CIPHER_TYPE_NO_CIPHER ((u32)-1)
398 …, IN const u32 cipher_type, IN const u32 auth_type,IN const void* pCipherKey, IN const u32 lenCiph…
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A Drtl8721d_i2c.h249 #define I2C_SS_MODE ((u32)0x00000001)
250 #define I2C_FS_MODE ((u32)0x00000002)
307 _LONG_CALL_ void I2C_INTConfig(I2C_TypeDef *I2Cx, u32 I2C_IT, u32 NewState);
309 _LONG_CALL_ void I2C_SetSpeed(I2C_TypeDef *I2Cx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk);
344 _LONG_CALL_ void I2C_DmaMode1Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen);
345 _LONG_CALL_ void I2C_DmaMode2Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen);
620 u32 Tx_HandshakeInterface;
621 u32 Rx_HandshakeInterface;
626 extern u32 I2C_SLAVEWRITE_PATCH;
627 extern u32 IC_FS_SCL_HCNT_TRIM;
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A Drtl8721d_rtc.h366 _LONG_CALL_ u32 RTC_BypassShadowCmd(u32 NewState);
370 _LONG_CALL_ u32 RTC_SetTime(u32 RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
373 _LONG_CALL_ u32 RTC_DayIntCmd(u32 NewState);
374 _LONG_CALL_ u32 RTC_DayThresSet(u32 DayThres);
376 _LONG_CALL_ u32 RTC_SetAlarm(u32 RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
381 _LONG_CALL_ u32 RTC_DayLightSavingConfig(u32 RTC_DayLightSaving, u32 RTC_StoreOperation);
383 _LONG_CALL_ u32 RTC_OutputConfig(u32 RTC_Output);
384 _LONG_CALL_ u32 RTC_SmoothCalibConfig(u32 CalibSign, u32 Value, u32 CalibPeriod, u32 Calib_Enable);
385 _LONG_CALL_ u32 RTC_32KAutoCalibConfig(u32 Cal_Period, u32 Unit_Sel);
401 #define RTC_TR_PM ((u32)0x00400000)
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A Drtl8721d_uart.h508 _LONG_CALL_ u32 UART_BaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
509 _LONG_CALL_ void UART_BaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
510 _LONG_CALL_ void UART_SetBaudExt(UART_TypeDef* UARTx, u32 Ovsr, u32 Ovsr_adj);
520 _LONG_CALL_ u32 UART_ReceiveDataTO(UART_TypeDef* UARTx, u8* OutBuf, u32 Count, u32 Times);
521 _LONG_CALL_ u32 UART_SendDataTO(UART_TypeDef* UARTx,u8* InBuf,u32 Count, u32 Times);
527 _LONG_CALL_ void UART_INTConfig(UART_TypeDef* UARTx, u32 UART_IT, u32 newState);
770 u32 Tx_HandshakeInterface;
783 UART_SetTxFlag(u32 UartIdx, u32 Flag) in UART_SetTxFlag()
789 UART_SetRxFlag(u32 UartIdx, u32 Flag) in UART_SetRxFlag()
794 static inline u32
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A Drtl8721d_audio.h114 #define SP_WL_16 ((u32)0x00000000)
115 #define SP_WL_24 ((u32)0x00000002)
116 #define SP_WL_8 ((u32)0x00000003)
129 #define SP_DF_I2S ((u32)0x00000000)
130 #define SP_DF_LEFT ((u32)0x00000001)
131 #define SP_DF_PCM_A ((u32)0x00000002)
132 #define SP_DF_PCM_B ((u32)0x00000003)
151 #define SP_CH_MONO ((u32)0x00000001)
163 #define SP_RX_CH_LR ((u32)0x00000000)
345 u32 Tx_HandshakeInterface;
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A Drtl8721d_ssi.h412 _LONG_CALL_ VOID SSI_INTConfig(SPI_TypeDef* spi_dev, u32 SSI_IT, u32 newState);
424 _LONG_CALL_ u32 SSI_ReceiveData(SPI_TypeDef *spi_dev, void* RxData, u32 Length);
425 _LONG_CALL_ u32 SSI_SendData(SPI_TypeDef *spi_dev, void* TxData, u32 Length, u32 Role);
433 _LONG_CALL_ void SSI_SetBaud(SPI_TypeDef *SPIx, u32 BaudRate, u32 IpClk);
447 _LONG_CALL_ void SSI_SetDmaEnable(SPI_TypeDef *spi_dev, u32 newState, u32 Mask);
448 _LONG_CALL_ void SSI_SetDmaLevel(SPI_TypeDef *spi_dev, u32 TxLeve, u32 RxLevel);
514 #define BIT_SER_SER ((u32)0x0000FFFF)
556 #define BIT_SR_BUSY ((u32)0x00000001)
636 #define BIT_DR_DR ((u32)0x0000FFFF)
659 u32 Tx_HandshakeInterface;
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A Drtl8721d_i2s.h163 #define I2S_WL_16 ((u32)0x00000000)
210 #define I2S_TXRX ((u32)0x00000002)
239 #define I2S_MUTE ((u32)0x00000001)
362 _LONG_CALL_ void I2S_INTConfig(I2S_TypeDef* I2Sx, u32 I2STxIntrMSK, u32 I2SRxIntrMSK);
372 _LONG_CALL_ void I2S_INTClear(I2S_TypeDef* I2Sx, u32 I2STxIntrClr, u32 I2SRxIntrClr);
374 _LONG_CALL_ void I2S_ISRGet(I2S_TypeDef* I2Sx, u32* I2STxIsr, u32* I2SRxIsr);
382 _LONG_CALL_ u32 I2S_TxPageBusy( I2S_TypeDef* I2Sx, u32 page_index);
383 _LONG_CALL_ void I2S_SetRxPageAddr( u32 page_index, u32 page_address);
384 _LONG_CALL_ void I2S_SetTxPageAddr( u32 page_index, u32 page_address);
386 _LONG_CALL_ u32 I2S_GetTxPageAddr( u32 page_index);
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A Drtl8721d_keyscan.h85 u32 KS_WorkMode; /*!< Specifies Keyscan work mode.
88 u32 KS_RowSel; /*!< Specifies which row(s) is used.
91 u32 KS_ColSel; /*!< Specifies which column(s) is used.
109 u32 KS_OverCtrl; /*!< Specifies Keyscan FIFO over control.
132 #define KS_REGULAR_SCAN_MODE ((u32)0x00000000 << 3)
133 #define KS_EVENT_TRIGGER_MODE ((u32)0x00000001 << 3)
143 #define KS_FIFO_OVER_CTRL_DIS_NEW ((u32)0x00000000 << 1)
144 #define KS_FIFO_OVER_CTRL_DIS_LAST ((u32)0x00000001 << 1)
184 _LONG_CALL_ u32 KeyScan_GetINT(KEYSCAN_TypeDef *KeyScan);
294 #define BIT_KS_ALL_INT_MSK ((u32)0x0000007f)
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A Drtl8721d_tim.h388 #define IS_TIM_IT(IT) ((((IT) & (u32)0xFFF80000) == 0x0000) && (((IT) & (u32)0x7FFFF) != 0x0000))
514 _LONG_CALL_ void RTIM_PrescalerConfig(RTIM_TypeDef* TIMx, u32 Prescaler, u32 TIM_PSCReloadMode);
534 _LONG_CALL_ void RTIM_SetOnePulseOutputMode(RTIM_TypeDef* TIMx, u32 TIM_OPMode, u32 TrigerPolarity);
542 _LONG_CALL_ void RTIM_INTConfig(RTIM_TypeDef* TIMx, u32 TIM_IT, u32 NewState);
545 _LONG_CALL_ u32 RTIM_GetFlagStatus(RTIM_TypeDef* TIMx, u32 TIM_FLAG);
546 _LONG_CALL_ u32 RTIM_GetINTStatus(RTIM_TypeDef* TIMx, u32 TIM_IT);
682 u32 PWM_CHANNEL;
683 u32 KM0_CHAN_STATUS;
684 u32 KM4_CHAN_STATUS;
692 extern u32 TIM_IT_CCx_LP[6];
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A Drtl8721d_ir.h345 void IR_Cmd(IR_TypeDef *IRx, u32 mode, u32 NewState);
346 void IR_SetRxCounterThreshold(IR_TypeDef *IRx, u32 IR_RxCntThrType, u32 IR_RxCntThr);
347 void IR_SendBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len, u32 IsLastPacket);
348 void IR_ReceiveBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len);
349 void IR_INTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState);
350 void IR_MaskINTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState);
351 u32 IR_GetINTStatus(IR_TypeDef *IRx);
352 u32 IR_GetIMR(IR_TypeDef *IRx);
353 u32 IR_FSMRunning(IR_TypeDef *IRx);
358 u32 IR_GetRxDataLen(IR_TypeDef *IRx);
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A Drtl8721d_psram.h149 u32 PCTL_clk_ps; /*!< Specifies the PSRAM clock cycle.
347 _LONG_CALL_ void PSRAM_CTRL_DPin_Mem(u8* PSRAM_CA, u32* PSRAM_data, u32 PSRAM_byteen, u8 RW);
349 _LONG_CALL_ u32 PSRAM_PHY_REG_Read(u8 offset);
477 #define BIT_PSRAM_MR0_BURST_RSVD_MASK ((u32)0x0000000f)
483 #define BIT_PSRAM_MR0_BURST_TYPE_MASK ((u32)0x00000001)
485 #define BIT_PSRAM_MR0_BURST_LENGTH_MASK ((u32)0x00000003)
495 #define BIT_PSRAM_MR1_REFRESH_RATE_MASK ((u32)0x00000001)
497 #define BIT_PSRAM_MR1_HALF_SLP_MODE_MASK ((u32)0x00000001)
499 #define BIT_PSRAM_MR1_PASR_MASK ((u32)0x00000007)
621 u32 psram_dev_enable; /*enable psram*/
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A Drtl8721d_captouch.h129 u32 CT_ETCFactor; /*!< Specifies CapTouch ETC Factor.
132 u32 CT_ETCScanInterval; /*!< Specifies ETC scan interval
205 u32 CapTouch_GetRawISR(CAPTOUCH_TypeDef *CapTouch);
206 u32 CapTouch_GetISR(CAPTOUCH_TypeDef *CapTouch);
210 u32 CapTouch_GetChStatus(CAPTOUCH_TypeDef *CapTouch, u32 Channel);
226 void CapTouch_DbgDumpETC(CAPTOUCH_TypeDef *CapTouch, u32 ch);
227 u32 CapTouch_DbgRawData(CAPTOUCH_TypeDef *CapTouch);
320 #define BIT_CT_ALL_INT_EN ((u32)0x00031f1f)
340 #define BIT_CT_ALL_INT_CLR_MASK ((u32)0x00071f1f)
356 #define BIT_MASK_CHX_N_ENT ((u32)0x000000ff << 24)
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A Drtl8721d_usi_uart.h487 _LONG_CALL_ u32 USI_UARTBaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
488 _LONG_CALL_ void USI_UARTBaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
489 _LONG_CALL_ void USI_UARTSetBaudExt(USI_TypeDef* USIx, u32 Ovsr, u32 Ovsr_adj);
499 _LONG_CALL_ u32 USI_UARTReceiveDataTO(USI_TypeDef* USIx, u8* OutBuf, u32 Count, u32 Times);
500 _LONG_CALL_ u32 USI_UARTSendDataTO(USI_TypeDef* USIx,u8* InBuf,u32 Count, u32 Times);
508 _LONG_CALL_ void USI_UARTINTConfig(USI_TypeDef* USIx, u32 UART_IT, u32 newState);
542 _LONG_CALL_ void USI_UARTLPRxBaudSet(USI_TypeDef* USIx, u32 BaudRate, u32 RxIPClockHz);
581 USI_UART_SetTxFlag(u32 USIIdx, u32 Flag) in USI_UART_SetTxFlag()
587 USI_UART_SetRxFlag(u32 USIIdx, u32 Flag) in USI_UART_SetRxFlag()
592 static inline u32
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A Drtl8721d_gdma.h345 #define MsizeOne ((u32)0x00000000)
346 #define MsizeFour ((u32)0x00000001)
362 #define IncType ((u32)0x00000000)
363 #define DecType ((u32)0x00000001)
364 #define NoChange ((u32)0x00000002)
377 #define BlockType ((u32)0x00000002)
450 _LONG_CALL_ void GDMA_INTConfig(u8 GDMA_Index, u8 GDMA_ChNum, u32 GDMA_IT, u32 NewState);
451 _LONG_CALL_ u32 GDMA_ClearINTPendingBit(u8 GDMA_Index, u8 GDMA_ChNum, u32 GDMA_IT);
464 _LONG_CALL_ u8 GDMA_ChnlAlloc(u32 GDMA_Index, IRQ_FUN IrqFun, u32 IrqData, u32 IrqPriority);
604 __STATIC_INLINE void GDMA_BurstEnable(u32 ch_num, u32 NewState) { in GDMA_BurstEnable()
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A Drtl8721d_usi_ssi.h362 _LONG_CALL_ void USI_SSI_TRxPath_Cmd(USI_TypeDef *usi_dev, u32 path, u32 NewStatus);
364 _LONG_CALL_ void USI_SSI_INTConfig(USI_TypeDef* usi_dev, u32 USI_SSI_IT, u32 newState);
372 _LONG_CALL_ void USI_SSI_SetBaud(USI_TypeDef *USIx, u32 BaudRate, u32 IpClk);
377 _LONG_CALL_ u32 USI_SSI_Writeable(USI_TypeDef *usi_dev);
379 _LONG_CALL_ u32 USI_SSI_ReadData(USI_TypeDef *usi_dev);
380 _LONG_CALL_ u32 USI_SSI_ReceiveData(USI_TypeDef *usi_dev, void* RxData, u32 Length);
381 _LONG_CALL_ u32 USI_SSI_SendData(USI_TypeDef *usi_dev, void* TxData, u32 Length, u32 Role);
388 _LONG_CALL_ u32 USI_SSI_Busy(USI_TypeDef *usi_dev);
389 _LONG_CALL_ u32 USI_SSI_GetIsr(USI_TypeDef *usi_dev);
403 _LONG_CALL_ void USI_SSI_SetDmaEnable(USI_TypeDef *usi_dev, u32 newState, u32 Mask);
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A Drtl8721d_crc.h66 u32 CRC_Type; /*!< Specifies CRC type
84 u32 CRC_DmaMode; /*!< Specifies CRC mode
99 #define CRC_TYPE_32 ((u32)0x00000000)
100 #define CRC_TYPE_24 ((u32)0x00000001)
101 #define CRC_TYPE_16 ((u32)0x00000002)
102 #define CRC_TYPE_12 ((u32)0x00000003)
103 #define CRC_TYPE_10 ((u32)0x00000004)
104 #define CRC_TYPE_8 ((u32)0x00000005)
105 #define CRC_TYPE_7 ((u32)0x00000006)
106 #define CRC_TYPE_5 ((u32)0x00000007)
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A Drtl8721d_otf.h49 _LONG_CALL_ void RSIP_Cmd(u32 NewStatus);
51 _LONG_CALL_ void RSIP_OTF_Cmd(u32 NewStatus);
52 _LONG_CALL_ void RSIP_OTF_Mask(u32 MaskIdx, u32 Addr, u32 Len, u32 NewStatus);
53 _LONG_CALL_ u32 RSIP_KEY_Request(u32 KeyTypeBit);
54 _LONG_CALL_ void RSIP_MMU_Config(u32 MMUIdx, u32 AddrStart, u32 AddrEnd, u32 IsMinus, u32 AddrOffse…
55 _LONG_CALL_ void RSIP_MMU_Cmd(u32 MMUIdx, u32 NewStatus);
82 #define OTF_FEN_OTFDEC ((u32)0x00000001) /*!<function enable of OTF decoder */
102 #define MMU_BIT_ENTRY_VALID ((u32)0x00000001) /*!< MMU entry_x valid */
112 #define RDP_KEY_REQUEST_TIMEOUT ((u32)0x00000003) /*!<Key request timeout */
113 #define RDP_NOT_ENABLE ((u32)0x00000004) /*!<RDP not enable in efuse */
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A Drtl8721d_pmc.h164 u32 km0_enable_key_touch;
167 u32 km0_pg_enable;
168 u32 km0_rtc_calibration;
172 u32 km0_fw_idle_time;
173 u32 km0_clk_down_time;
174 u32 km0_rf_off_time;
175 u32 km0_gating_time;
176 u32 km0_rf_on_time;
177 u32 km0_wake_time;
178 u32 km0_dur1;
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A Drtl8721d_gpio.h235 _LONG_CALL_ void GPIO_WriteBit(u32 GPIO_Pin, u32 BitVal);
236 _LONG_CALL_ u32 GPIO_ReadDataBit(u32 GPIO_Pin);
237 _LONG_CALL_ void GPIO_DeInit(u32 GPIO_Pin);
239 _LONG_CALL_ void GPIO_INTMode(u32 GPIO_Pin, u32 NewState, u32 GPIO_ITTrigger, u32 GPIO_ITPolarity, …
240 _LONG_CALL_ void GPIO_INTConfig(u32 GPIO_Pin, u32 NewState);
242 _LONG_CALL_ u32 GPIO_INTHandler(IN VOID *pData);
243 _LONG_CALL_ void GPIO_Direction(u32 GPIO_Pin, u32 data_direction);
244 _LONG_CALL_ u32 GPIO_PortRead(u32 GPIO_Port, u32 GPIO_Mask);
245 _LONG_CALL_ void GPIO_PortWrite(u32 GPIO_Port, u32 GPIO_Mask, u32 Port_State);
246 _LONG_CALL_ void GPIO_PortDirection(u32 GPIO_Port, u32 GPIO_Mask, u32 data_direction);
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/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/common/drivers/wlan/realtek/include/
A Dwifi_performance_monitor.h12 u32 rx_mpdu_time;
13 u32 rx_mpdu_time1;
14 u32 rx_mpdu_time2;
16 u32 recv_entry_time;
18 u32 recv_func_time;
36 u32 netif_rx_time;
43 u32 wlan_send_time;
44 u32 wlan_send_time1;
51 u32 xmit_time;
52 u32 xmit_time1;
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/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/common/network/ssl/ssl_ram_map/rom/
A Drom_ssl_ram_map.h16 const u8* iv, const u32 ivlen,
20 const u8* iv, const u32 ivlen,
25 const u8* iv, const u32 ivlen,
29 const u8* iv, const u32 ivlen,
36 const u8* iv, const u32 ivlen,
40 const u8* iv, const u32 ivlen,
45 const u8* iv, const u32 ivlen,
49 const u8* iv, const u32 ivlen,
53 u32 use_hw_crypto_func;
66 const u8* iv, const u32 ivlen,
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