1 /*
2  * Renesas SCP/MCP Software
3  * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights
4  * reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef ARMV8A_GIC_H
10 #define ARMV8A_GIC_H
11 
12 #include <fwk_arch.h>
13 
14 #include <arch_helpers.h>
15 
16 /* Constants to categorise priorities */
17 #define GIC_HIGHEST_SEC_PRIORITY 0x0
18 #define GIC_LOWEST_SEC_PRIORITY 0x7f
19 #define GIC_HIGHEST_NS_PRIORITY 0x80
20 #define GIC_LOWEST_NS_PRIORITY 0xfe /* 0xff would disable all interrupts */
21 
22 /*******************************************************************************
23  * GIC Distributor interface general definitions
24  ******************************************************************************/
25 /* Constants to categorise interrupts */
26 #define MIN_SGI_ID U(0)
27 #define MIN_SEC_SGI_ID U(8)
28 #define MIN_PPI_ID U(16)
29 #define MIN_SPI_ID U(32)
30 #define MAX_SPI_ID U(1019)
31 
32 /* Mask for the priority field common to all GIC interfaces */
33 #define GIC_PRI_MASK U(0xff)
34 
35 /* Mask for the configuration field common to all GIC interfaces */
36 #define GIC_CFG_MASK U(0x3)
37 
38 /*******************************************************************************
39  * GIC Distributor interface register offsets that are common to GICv2
40  ******************************************************************************/
41 #define GICD_CTLR U(0x0)
42 #define GICD_TYPER U(0x4)
43 #define GICD_IIDR U(0x8)
44 #define GICD_IGROUPR U(0x80)
45 #define GICD_ISENABLER U(0x100)
46 #define GICD_ICENABLER U(0x180)
47 #define GICD_ISPENDR U(0x200)
48 #define GICD_ICPENDR U(0x280)
49 #define GICD_ISACTIVER U(0x300)
50 #define GICD_ICACTIVER U(0x380)
51 #define GICD_IPRIORITYR U(0x400)
52 #define GICD_ITARGETSR U(0x800)
53 #define GICD_ICFGR U(0xc00)
54 #define GICD_NSACR U(0xe00)
55 
56 /* GICD_CTLR bit definitions */
57 #define CTLR_ENABLE_G0_SHIFT 0
58 #define CTLR_ENABLE_G0_MASK U(0x1)
59 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
60 #define CTLR_ENABLE_G1_SHIFT 1
61 #define CTLR_ENABLE_G1_MASK U(0x1)
62 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
63 
64 /*******************************************************************************
65  * GICv2 specific CPU interface register offsets and constants.
66  ******************************************************************************/
67 /* Physical CPU Interface registers */
68 #define GICC_CTLR U(0x0)
69 #define GICC_PMR U(0x4)
70 #define GICC_BPR U(0x8)
71 #define GICC_IAR U(0xC)
72 #define GICC_EOIR U(0x10)
73 #define GICC_RPR U(0x14)
74 #define GICC_HPPIR U(0x18)
75 #define GICC_AHPPIR U(0x28)
76 #define GICC_IIDR U(0xFC)
77 #define GICC_DIR U(0x1000)
78 #define GICC_PRIODROP GICC_EOIR
79 
80 /* Common CPU Interface definitions */
81 #define INT_ID_MASK U(0x3ff)
82 #define INT_ID(n) (n & INT_ID_MASK)
83 
84 /* GICC_CTLR bit definitions */
85 #define EOI_MODE_NS (U(1) << 10)
86 #define EOI_MODE_S (U(1) << 9)
87 #define IRQ_BYP_DIS_GRP1 (U(1) << 8)
88 #define FIQ_BYP_DIS_GRP1 (U(1) << 7)
89 #define IRQ_BYP_DIS_GRP0 (U(1) << 6)
90 #define FIQ_BYP_DIS_GRP0 (U(1) << 5)
91 #define CBPR (U(1) << 4)
92 #define FIQ_EN (U(1) << 3)
93 #define ACK_CTL (U(1) << 2)
94 #define ENABLE_G1 (U(1) << 1)
95 #define ENABLE_G0 (U(1) << 0)
96 #define FIQ_EN_SHIFT 3
97 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
98 
99 /*******************************************************************************
100  * GIC Distributor interface register constants that are common to GICv3 & GICv2
101  ******************************************************************************/
102 #define PIDR2_ARCH_REV_SHIFT 4
103 #define PIDR2_ARCH_REV_MASK U(0xf)
104 
105 /* GICv3 revision as reported by the PIDR2 register */
106 #define ARCH_REV_GICV3 U(0x3)
107 /* GICv2 revision as reported by the PIDR2 register */
108 #define ARCH_REV_GICV2 U(0x2)
109 /* GICv1 revision as reported by the PIDR2 register */
110 #define ARCH_REV_GICV1 U(0x1)
111 
112 #define IGROUPR_SHIFT 5
113 #define ISENABLER_SHIFT 5
114 #define ICENABLER_SHIFT ISENABLER_SHIFT
115 #define ISPENDR_SHIFT 5
116 #define ICPENDR_SHIFT ISPENDR_SHIFT
117 #define ISACTIVER_SHIFT 5
118 #define ICACTIVER_SHIFT ISACTIVER_SHIFT
119 #define IPRIORITYR_SHIFT 2
120 #define ITARGETSR_SHIFT 2
121 #define ICFGR_SHIFT 4
122 #define NSACR_SHIFT 4
123 
124 /* GIC */
125 #define RCAR_GICD_BASE U(0xF1010000)
126 #define RCAR_GICR_BASE U(0xF1010000)
127 #define RCAR_GICC_BASE U(0xF1020000)
128 #define RCAR_GICH_BASE U(0xF1040000)
129 #define RCAR_GICV_BASE U(0xF1060000)
130 
131 void gic_init(void);
132 int arm_gic_init(const struct fwk_arch_interrupt_driver **driver);
133 void irq_global(uint32_t iid);
134 
135 #endif /* ARMV8A_GIC_H */
136