Searched refs:CLKDIV (Results 1 – 2 of 2) sorted by relevance
21 #define CLKDIV ((SYSINCLK / (DDR_FREQUENCY_MHZ * FWK_MHZ)) - 1) macro
54 (CLKDIV << 16)); in ddr_clock_div_set_check()138 fwk_assert(CLKDIV <= 16); in ddr_clock_div_set()139 fwk_assert(CLKDIV != 0); in ddr_clock_div_set()142 (SCP_CONFIG->DMCCLK_CONTROL & ~DMCCLK_CONTROL_CLKDIV) | (CLKDIV << 4); in ddr_clock_div_set()979 fwk_assert(CLKDIV > 0); in juno_dmc400_start()
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