Searched refs:CLK_PLL1 (Results 1 – 2 of 2) sorted by relevance
18 CLK_PLL1, enumerator
341 module_ctx.parent_clk[CLK_PLL1] = r8a7795_cpg_pll1_init(ext->ext_clk_rate); in sd_clock_init()342 module_ctx.parent_clk[CLK_PLL1_DIV2] = module_ctx.parent_clk[CLK_PLL1] / 2; in sd_clock_init()343 module_ctx.parent_clk[CLK_PLL1_DIV4] = module_ctx.parent_clk[CLK_PLL1] / 4; in sd_clock_init()
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