Searched refs:CLK_PLL1_DIV4 (Results 1 – 3 of 3) sorted by relevance
20 CLK_PLL1_DIV4, enumerator
480 .parent = CLK_PLL1_DIV4,513 .parent = CLK_PLL1_DIV4,528 .parent = CLK_PLL1_DIV4,543 .parent = CLK_PLL1_DIV4,558 .parent = CLK_PLL1_DIV4,
343 module_ctx.parent_clk[CLK_PLL1_DIV4] = module_ctx.parent_clk[CLK_PLL1] / 4; in sd_clock_init()
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