1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Use of "manager" may be out of sync with older versions of TRM */ 9 10 #ifndef INTERNAL_SYNQUACER_PD_H 11 #define INTERNAL_SYNQUACER_PD_H 12 13 #include <ppu_v0.h> 14 15 #include <internal/reset.h> 16 17 #define PD_TIMEOUT_MS 200 18 #define PD_CHECK_CYCLE_MS 1 19 20 #define OFFCHIP_CYCLE_MS_PCIE 10 21 #define OFFCHIP_CYCLE_MS_DDR 10 22 23 #define DEV_BMAP_CA53(cluster) (1 << (cluster + 16)) 24 #define DEV_BMAP_CA53_ALL 0x0FFF0000 25 #define DEV_BMAP_DDR0 0x00001000 26 #define DEV_BMAP_DDR1 0x00002000 27 #define DEV_BMAP_PCIE_BLK 0x00000800 28 #define DEV_BMAP_PCIE0 0x00000100 29 #define DEV_BMAP_PCIE1 0x00000200 30 31 #define DEV_BMAP_SCB_AM 0x00000001 32 #define DEV_BMAP_SCB_SUBSYS 0x00000004 33 #define DEV_BMAP_DMA_BLK 0x00000010 34 //#define DEV_BMAP_SCB_TOP 0x00000002 /* can't change now */ 35 //#define DEV_BMAP_FE_TOP 0x00000008 /* can't change now */ 36 37 #define PD_PRESET_ALL 0x0FFF3B15 38 #define PD_PRESET_ALL_WO_CA53 (PD_PRESET_ALL & ~(DEV_BMAP_CA53_ALL)) 39 40 #define PD_PRESET_COLDBOOT PD_PRESET_ALL 41 42 #define PD_PRESET_CM3_REBOOT PD_PRESET_ALL 43 #define PD_PRESET_AP_REBOOT \ 44 (PD_PRESET_CM3_REBOOT & ~(DEV_BMAP_SCB_SUBSYS | DEV_BMAP_PCIE_BLK)) 45 46 #define PD_PRESET_AP_REBOOT_WO_PCIE0 (PD_PRESET_AP_REBOOT & ~(DEV_BMAP_PCIE0)) 47 #define PD_PRESET_AP_REBOOT_WO_PCIE1 (PD_PRESET_AP_REBOOT & ~(DEV_BMAP_PCIE1)) 48 49 #define PD_PRESET_SHUTDOWN PD_PRESET_ALL 50 51 #define NOT_USE (-1) 52 53 #define CLUSTER_PMU_NO(no) (19 + no) 54 #define OFFCHIP_PCIE_PMU_NO(no) (10 + no) 55 #define OFFCHIP_DDR_PMU_NO(no) (12 + no) 56 #define ONCHIP_PCIE_PMU_NO(no) (14 + no) 57 #define ONCHIP_DDR_PMU_NO(no) (16 + no) 58 59 #define SNI_PPU_INFO_MP \ 60 { \ 61 { \ 62 /* "DDRPHY_BLK_0" */ /* no */ 2, \ 63 /* dev_bitmap */ DEV_BMAP_DDR0, \ 64 /* booting_force_off */ false, \ 65 /* force_off */ false, \ 66 }, \ 67 { \ 68 /* "DDRPHY_BLK_1" */ /* no */ 3, \ 69 /* dev_bitmap */ DEV_BMAP_DDR1, \ 70 /* booting_force_off */ false, \ 71 /* force_off */ false, \ 72 }, \ 73 { \ 74 /* "PCIEB" */ /* no */ 4, \ 75 /* dev_bitmap */ DEV_BMAP_PCIE_BLK, \ 76 /* booting_force_off */ false, \ 77 /* force_off */ false, \ 78 }, \ 79 { \ 80 /* "PCIE_BLK_0" */ /* no */ 6, \ 81 /* dev_bitmap */ DEV_BMAP_PCIE0, \ 82 /* booting_force_off */ false, \ 83 /* force_off */ false, \ 84 }, \ 85 { \ 86 /* "PCIE_BLK_1" */ /* no */ 5, \ 87 /* dev_bitmap */ DEV_BMAP_PCIE1, \ 88 /* booting_force_off */ false, \ 89 /* force_off */ false, \ 90 }, \ 91 { \ 92 /* "DMAB" */ /* no */ 7, \ 93 /* dev_bitmap */ DEV_BMAP_DMA_BLK, \ 94 /* booting_force_off */ false, \ 95 /* force_off */ false, \ 96 }, \ 97 { \ 98 /* "SCB_A_MANAGER" */ /* no */ 8, \ 99 /* dev_bitmap */ DEV_BMAP_SCB_AM, \ 100 /* booting_force_off */ true, \ 101 /* force_off */ true, \ 102 }, \ 103 } 104 105 #define TRANSW_NO_PCIE 0 106 #define TRANSW_NO_SCBM 1 107 #define TRANSW_NO_CM3 2 108 #define TRANSW_NO_DDR 3 109 110 #define TRANSW_REG_NUM 4 111 112 #define SNI_TRANSACTIONSW_INFO_MP \ 113 { \ 114 { \ 115 /* "PCIe#0" */ /* dev_bitmap */ DEV_BMAP_PCIE0, \ 116 /* reg_no */ TRANSW_NO_PCIE, \ 117 /* sw_bitmap */ 0x2, \ 118 }, \ 119 { \ 120 /* "PCIe#1" */ /* dev_bitmap */ DEV_BMAP_PCIE1, \ 121 /* reg_no */ TRANSW_NO_PCIE, \ 122 /* sw_bitmap */ 0x1, \ 123 }, \ 124 { \ 125 /* "SCBM" */ /* dev_bitmap */ DEV_BMAP_SCB_AM, \ 126 /* reg_no */ TRANSW_NO_SCBM, \ 127 /* sw_bitmap */ 0x7, \ 128 }, \ 129 { \ 130 /* "CM3" */ /* dev_bitmap */ DEV_BMAP_SCB_SUBSYS, \ 131 /* reg_no */ TRANSW_NO_CM3, \ 132 /* sw_bitmap */ 0x7, \ 133 }, \ 134 { \ 135 /* "DDR#0" */ /* dev_bitmap */ DEV_BMAP_DDR0, \ 136 /* reg_no */ TRANSW_NO_DDR, \ 137 /* sw_bitmap */ 0x1, \ 138 }, \ 139 { \ 140 /* "DDR#1" */ /* dev_bitmap */ DEV_BMAP_DDR1, \ 141 /* reg_no */ TRANSW_NO_DDR, \ 142 /* sw_bitmap */ 0x2, \ 143 }, \ 144 } 145 146 #ifdef CONFIG_SCB_DIST_FIRM 147 #define PD_REBOOT_DEV_BITMAP PD_PRESET_AP_REBOOT_WO_PCIE0 148 #else /* CONFIG_SCB_DIST_FIRM */ 149 #define PD_REBOOT_DEV_BITMAP PD_PRESET_AP_REBOOT 150 #endif /* CONFIG_SCB_DIST_FIRM */ 151 152 #define SNI_PMU_INFO_MP \ 153 { \ 154 { \ 155 /* [0]: "SCB_AM" */ /* on_priority */ 0, \ 156 /* dev_bitmap */ DEV_BMAP_SCB_AM, \ 157 /* onchip_pd */ 18, \ 158 /* offchip_pd */ NOT_USE, \ 159 /* offchip_cycle_ms */ 0, \ 160 }, \ 161 { \ 162 /* [1]: "SCB_Subsys" */ /* on_priority */ 0, \ 163 /* dev_bitmap */ DEV_BMAP_SCB_SUBSYS, \ 164 /* onchip_pd */ 31, \ 165 /* offchip_pd */ NOT_USE, \ 166 /* offchip_cycle_ms */ 0, \ 167 }, \ 168 { \ 169 /* [2]: "Cluster#0(A)" */ /* on_priority */ 1, \ 170 /* dev_bitmap */ DEV_BMAP_CA53(0), \ 171 /* onchip_pd */ 19, \ 172 /* offchip_pd */ NOT_USE, \ 173 /* offchip_cycle_ms */ 0, \ 174 }, \ 175 { \ 176 /* [3]: "Cluster#5(A)" */ /* on_priority */ 1, \ 177 /* dev_bitmap */ DEV_BMAP_CA53(5), \ 178 /* onchip_pd */ 24, \ 179 /* offchip_pd */ NOT_USE, \ 180 /* offchip_cycle_ms */ 0, \ 181 }, \ 182 { \ 183 /* [4]: "Cluster#9(A)" */ /* on_priority */ 1, \ 184 /* dev_bitmap */ DEV_BMAP_CA53(9), \ 185 /* onchip_pd */ 28, \ 186 /* offchip_pd */ NOT_USE, \ 187 /* offchip_cycle_ms */ 0, \ 188 }, \ 189 { \ 190 /* [5]: "Cluster#10(A)" */ /* on_priority */ 1,\ 191 /* dev_bitmap */ DEV_BMAP_CA53(10), \ 192 /* onchip_pd */ 29, \ 193 /* offchip_pd */ NOT_USE, \ 194 /* offchip_cycle_ms */ 0, \ 195 }, \ 196 { \ 197 /* [6]: "Cluster#1(B)" */ /* on_priority */ 2, \ 198 /* dev_bitmap */ DEV_BMAP_CA53(1), \ 199 /* onchip_pd */ 20, \ 200 /* offchip_pd */ NOT_USE, \ 201 /* offchip_cycle_ms */ 0, \ 202 }, \ 203 { \ 204 /* [7]: "Cluster#6(B)" */ /* on_priority */ 2, \ 205 /* dev_bitmap */ DEV_BMAP_CA53(6), \ 206 /* onchip_pd */ 25, \ 207 /* offchip_pd */ NOT_USE, \ 208 /* offchip_cycle_ms */ 0, \ 209 }, \ 210 { \ 211 /* [8]: "Cluster#7(B)" */ /* on_priority */ 2, \ 212 /* dev_bitmap */ DEV_BMAP_CA53(7), \ 213 /* onchip_pd */ 26, \ 214 /* offchip_pd */ NOT_USE, \ 215 /* offchip_cycle_ms */ 0, \ 216 }, \ 217 { \ 218 /* [9]: "Cluster#11(B)" */ /* on_priority */ 2,\ 219 /* dev_bitmap */ DEV_BMAP_CA53(11), \ 220 /* onchip_pd */ 30, \ 221 /* offchip_pd */ NOT_USE, \ 222 /* offchip_cycle_ms */ 0, \ 223 }, \ 224 { \ 225 /* [10]: "Cluster#2(C)" */ /* on_priority */ 3,\ 226 /* dev_bitmap */ DEV_BMAP_CA53(2), \ 227 /* onchip_pd */ 21, \ 228 /* offchip_pd */ NOT_USE, \ 229 /* offchip_cycle_ms */ 0, \ 230 }, \ 231 { \ 232 /* [11]: "Cluster#3(C)" */ /* on_priority */ 3,\ 233 /* dev_bitmap */ DEV_BMAP_CA53(3), \ 234 /* onchip_pd */ 22, \ 235 /* offchip_pd */ NOT_USE, \ 236 /* offchip_cycle_ms */ 0, \ 237 }, \ 238 { \ 239 /* [12]: "Cluster#4(C)" */ /* on_priority */ 3,\ 240 /* dev_bitmap */ DEV_BMAP_CA53(4), \ 241 /* onchip_pd */ 23, \ 242 /* offchip_pd */ NOT_USE, \ 243 /* offchip_cycle_ms */ 0, \ 244 }, \ 245 { \ 246 /* [13]: "Cluster#8(C)" */ /* on_priority */ 3,\ 247 /* dev_bitmap */ DEV_BMAP_CA53(8), \ 248 /* onchip_pd */ 27, \ 249 /* offchip_pd */ NOT_USE, \ 250 /* offchip_cycle_ms */ 0, \ 251 }, \ 252 { \ 253 /* [14]: "DDR#0" */ /* on_priority */ 4, \ 254 /* dev_bitmap */ DEV_BMAP_DDR0, \ 255 /* onchip_pd */ 16, \ 256 /* offchip_pd */ 12, \ 257 /* offchip_cycle_ms */ OFFCHIP_CYCLE_MS_DDR, \ 258 }, \ 259 { \ 260 /* [15]: "DDR#1" */ /* on_priority */ 5, \ 261 /* dev_bitmap */ DEV_BMAP_DDR1, \ 262 /* onchip_pd */ 17, \ 263 /* offchip_pd */ 13, \ 264 /* offchip_cycle_ms */ OFFCHIP_CYCLE_MS_DDR, \ 265 },\ 266 { \ 267 /* [16]: "PCIe#0" */ /* on_priority */ 6, \ 268 /* dev_bitmap */ DEV_BMAP_PCIE0, \ 269 /* onchip_pd */ 15, \ 270 /* offchip_pd */ 11, \ 271 /* offchip_cycle_ms */ OFFCHIP_CYCLE_MS_PCIE, \ 272 }, \ 273 { \ 274 /* [17]: "PCIe#1" */ /* on_priority */ 7, \ 275 /* dev_bitmap */ DEV_BMAP_PCIE1, \ 276 /* onchip_pd */ 14, \ 277 /* offchip_pd */ 10, \ 278 /* offchip_cycle_ms */ OFFCHIP_CYCLE_MS_PCIE, \ 279 }, \ 280 } 281 282 int32_t get_cluster_pmu_no(struct ppu_v0_reg *ppu); 283 uint32_t pmu_wait(uint32_t pmu_bitmap, bool on); 284 void power_domain_coldboot(void); 285 void power_domain_reboot(void); 286 287 #endif /* INTERNAL_SYNQUACER_PD_H */ 288