1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CPU_PIK_H 9 #define CPU_PIK_H 10 11 #include "scp_css_mmap.h" 12 13 #include <fwk_macros.h> 14 15 #include <stdint.h> 16 17 struct pik_cpu_reg { 18 uint8_t RESERVED0[0x10 - 0x00]; 19 FWK_RW uint32_t PE_STATIC_CONFIG; 20 uint32_t RESERVED1; 21 FWK_RW uint32_t PE_RVBARADDR_LW; 22 FWK_RW uint32_t PE_RVBARADDR_UP; 23 uint8_t RESERVED2[0x030-0x020]; 24 FWK_R uint32_t PE_STATUS; 25 uint8_t RESERVED3[0x800-0x034]; 26 FWK_RW uint32_t CLUS_PPUCLK_CTRL; 27 FWK_RW uint32_t CLUS_PPUCLK_DIV1; 28 uint8_t RESERVED4[0x840 - 0x808]; 29 FWK_RW uint32_t CLUS_GICCLK_CTRL; 30 FWK_RW uint32_t CLUS_GICCLK_DIV1; 31 uint8_t RESERVED5[0x850 -0x848]; 32 FWK_RW uint32_t CLUS_PERIPHCLK_CTRL; 33 FWK_RW uint32_t CLUS_PERIPHCLK_DIV1; 34 uint8_t RESERVED6[0x860 - 0x858]; 35 FWK_RW uint32_t CORECLK_CTRL; 36 FWK_RW uint32_t CORECLK_DIV1; 37 FWK_RW uint32_t CORECLK_MOD1; 38 uint8_t RESERVED7[0xA00 - 0x086C]; 39 FWK_RW uint32_t CLKFORCE_STATUS; 40 FWK_RW uint32_t CLKFORCE_SET; 41 FWK_RW uint32_t CLKFORCE_CLR; 42 uint8_t RESERVED8[0x0FB4 - 0x0A0C]; 43 FWK_R uint32_t CAP3; 44 FWK_R uint32_t CAP2; 45 FWK_R uint32_t CAP1; 46 FWK_R uint32_t PWR_CTRL_CONFIG; 47 uint8_t RESERVED9[0xFD0 - 0xFC4]; 48 FWK_R uint32_t PID4; 49 FWK_R uint32_t PID5; 50 FWK_R uint32_t PID6; 51 FWK_R uint32_t PID7; 52 FWK_R uint32_t PID0; 53 FWK_R uint32_t PID1; 54 FWK_R uint32_t PID2; 55 FWK_R uint32_t PID3; 56 FWK_R uint32_t ID0; 57 FWK_R uint32_t ID1; 58 FWK_R uint32_t ID2; 59 FWK_R uint32_t ID3; 60 }; 61 62 #define CLUSTER_PIK_PTR(IDX) ((struct pik_cpu_reg *)SCP_PIK_CLUSTER_BASE(IDX)) 63 64 #endif /* CPU_PIK_H */ 65