1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SYNQUACER_MMAP_H 9 #define SYNQUACER_MMAP_H 10 11 #include "synquacer_common.h" 12 #include "synquacer_pik.h" 13 14 #define PERIPH_BASE UINT32_C(0x44000000) 15 #define POWER_PERIPH_BASE UINT32_C(0x50000000) 16 #define EXTERNAL_DEV_BASE UINT32_C(0xA0000000) 17 18 #define TRUSTED_RAM_BASE (EXTERNAL_DEV_BASE + 0x04000000) 19 #define NIC_BASE (EXTERNAL_DEV_BASE + 0x2A100000) 20 #define REFCLK_CNTCONTROL_BASE (EXTERNAL_DEV_BASE + 0x2A430000) 21 #define REFCLK_CNTREAD_BASE (EXTERNAL_DEV_BASE + 0x2A800000) 22 #define DDR_WINDOW_BASE (EXTERNAL_DEV_BASE + 0x2B000000) 23 #define NONTRUSTED_RAM_BASE (EXTERNAL_DEV_BASE + 0x2E000000) 24 25 #define DDR_WINDOW_SIZE UINT32_C(0x100000) 26 27 #define REFCLK_CNTCTL_BASE (PERIPH_BASE + 0x0000) 28 #define REFCLK_CNTBASE0_BASE (PERIPH_BASE + 0x1000) 29 #ifdef CONFIG_SCB_USE_AP_PL011 30 #define SCP_UART_BASE UINT32_C(0xCA400000) 31 #else 32 #define SCP_UART_BASE (PERIPH_BASE + 0x2000) 33 #endif 34 #define WDOG_BASE (PERIPH_BASE + 0x6000) 35 #define MHU_AP_BASE (PERIPH_BASE + 0x1000000) 36 37 #define REFCLK_CNTCONTROL ((cntcontrol_reg_t *)REFCLK_CNTCONTROL_BASE) 38 #define REFCLK_CNTCTL ((cntctl_reg_t *)REFCLK_CNTCTL_BASE) 39 #define REFCLK_CNTBASE0 ((cntbase_reg_t *)REFCLK_CNTBASE0_BASE) 40 #define WDOG ((sp805_reg_t *)WDOG_BASE) 41 42 #define MHU_SCP_TO_AP_NS(cluster) \ 43 ((uintptr_t)(MHU_AP_BASE + 0x00010000 * cluster + 0x00000020)) 44 #define MHU_AP_TO_SCP_NS(cluster) \ 45 ((uintptr_t)(MHU_AP_BASE + 0x00010000 * cluster + 0x00000120)) 46 #define MHU_SCP_TO_AP_S(cluster) \ 47 ((uintptr_t)(MHU_AP_BASE + 0x00010000 * cluster + 0x00000200)) 48 #define MHU_AP_TO_SCP_S(cluster) \ 49 ((uintptr_t)(MHU_AP_BASE + 0x00010000 * cluster + 0x00000300)) 50 51 /* 52 * MHU secure/non-secure SRAM 53 */ 54 #define MHU_CLUSTER_PAYLOAD_INTERVAL (64 * 1024) 55 #define MHU_PAYLOAD_SIZE (256) 56 #define MHU_PAYLOAD_NS_BASE (PERIPH_BASE + 0x01200000) 57 #define MHU_PAYLOAD_S_BASE (PERIPH_BASE + 0x01400000) 58 59 #define MHU_PAYLOAD_S_CLUSTER_BASE(cluster) \ 60 (MHU_PAYLOAD_S_BASE + MHU_CLUSTER_PAYLOAD_INTERVAL * cluster) 61 /* 62 * Context area used by trusted firmware. Should be zeroed by SCP. 63 */ 64 #define AP_CONTEXT_BASE (TRUSTED_RAM_BASE + 0x0003F000) 65 #define AP_CONTEXT_SIZE 8 66 67 #define CCN512_BASE (EXTERNAL_DEV_BASE + 0x32000000) 68 69 #define CONFIG_SOC_CORE_CLOCK UINT32_C(125000000) 70 #define CONFIG_SCB_TICK_US 500 71 72 /* SynQuacer peripheral address */ 73 #define HSSPI_REG_BASE UINT32_C(0x48800000) 74 #define HSSPI_MEM_BASE UINT32_C(0xA8000000) 75 76 #define CONFIG_SOC_REG_ADDR_PBC_TOP UINT32_C(0x48900000) 77 #define CONFIG_SOC_REG_ADDR_PMU_TOP UINT32_C(0x48130000) 78 79 #define CONFIG_SOC_HSSPI_EEPROM_BASE_ADDR UINT32_C(0x48810000) 80 #define CONFIG_SOC_BOOT_HSSPI_REG_ADDR UINT32_C(0x48100008) 81 82 #define CONFIG_SCP_CONFIG_TABLE_ADDR UINT32_C(0xA8080000) 83 #define CONFIG_SCP_CONFIG_TABLE_OFFSET (CONFIG_SCP_CONFIG_TABLE_ADDR - \ 84 HSSPI_MEM_BASE) 85 86 /* EEPROM CONFIG */ 87 #define CONFIG_SCB_EEPROM_SIZE UINT32_C(65536) 88 #define CONFIG_SCP_CONFIG_TABLE_MAX_SIZE UINT32_C(65536) 89 90 #define CONFIG_SOC_REG_ADDR_SYSOC_TOP UINT32_C(0x48300000) 91 #define CONFIG_SOC_REG_ADDR_BOOT_CTL_TOP UINT32_C(0x48100000) 92 #define CONFIG_SOC_REG_ADDR_CFG_CTL_TOP UINT32_C(0x48110000) 93 #define CONFIG_SOC_REG_ADDR_XCPB_TOP UINT32_C(0x48160000) 94 95 #define AP_SCP_NIC UINT32_C(0x70100000) 96 #define DDRPHYREG0_NIC UINT32_C(0x7f000000) 97 #define DDRPHYREG1_NIC UINT32_C(0x7f400000) 98 #define DMABREG_NIC UINT32_C(0x7f800000) 99 #define FE_NIC UINT32_C(0x75000000) 100 #define SCBM_MV_NIC UINT32_C(0x72600000) 101 102 #define CONFIG_SOC_NIC_ADDR_INFO \ 103 { \ 104 NIC_BASE, AP_SCP_NIC, DDRPHYREG0_NIC, DDRPHYREG1_NIC, DMABREG_NIC, \ 105 FE_NIC, \ 106 } 107 108 #define CONFIG_SCB_NIC_INFO \ 109 { \ 110 { /* NIC_BASE */ \ 111 NIC_SETUP_SKIP, NIC_SETUP_SKIP, NIC_SETUP_SKIP, \ 112 NIC_SETUP_SKIP, NIC_SETUP_SKIP, 1, \ 113 END_OF_NIC_LIST \ 114 }, \ 115 { /* AP_SCP_NIC */ \ 116 1, \ 117 END_OF_NIC_LIST \ 118 }, \ 119 { /* DDRPHYREG0_NIC */ \ 120 3, \ 121 END_OF_NIC_LIST \ 122 }, \ 123 { /* DDRPHYREG1_NIC */ \ 124 3, \ 125 END_OF_NIC_LIST \ 126 }, \ 127 { /* DMABREG_NIC */ \ 128 NIC_SETUP_SKIP, \ 129 1, \ 130 END_OF_NIC_LIST \ 131 }, \ 132 { /* FE_NIC */ \ 133 NIC_SETUP_SKIP, \ 134 NIC_SETUP_SKIP, \ 135 1, \ 136 1, \ 137 END_OF_NIC_LIST \ 138 }, \ 139 } 140 141 /* CRG config */ 142 #define CONFIG_SOC_CRG11_NUM 2 143 #define CONFIG_SCB_CRG11_ID_PERI 0 144 #define CONFIG_SCB_CRG11_ID_EMMC 1 145 146 #define CONFIG_SOC_REG_ADDR_CRG_PERI_TOP UINT32_C(0x48310000) 147 #define CONFIG_SOC_REG_ADDR_CRG_EMMC_TOP UINT32_C(0x48320000) 148 149 #define F_UART3_BASE_ADDR UINT32_C(0x71040000) 150 #define CONFIG_SCB_UART_BAUD_RATE UART_SYSPARAM_BAUD_RATE_115200 151 152 #define CONFIG_SOC_REG_ADDR_SYSOC_TOP UINT32_C(0x48300000) 153 #define CONFIG_SOC_REG_ADDR_SYSOC_BUS_TOP CONFIG_SOC_REG_ADDR_SYSOC_TOP 154 #define CONFIG_SOC_REG_ADDR_SYSOC_SCP_TOP (CONFIG_SOC_REG_ADDR_SYSOC_TOP + 0x10) 155 #define CONFIG_SOC_REG_ADDR_SYSOC_DMA_TOP (CONFIG_SOC_REG_ADDR_SYSOC_TOP + 0x40) 156 #define CONFIG_SOC_REG_ADDR_SYSOC_PCIE_TOP \ 157 (CONFIG_SOC_REG_ADDR_SYSOC_TOP + 0x50) 158 #define CONFIG_SOC_REG_ADDR_SYSOC_DDR_TOP (CONFIG_SOC_REG_ADDR_SYSOC_TOP + 0x60) 159 160 #define CONFIG_SOC_INIT_SYSOC_ADDR_INFOS \ 161 { \ 162 CONFIG_SOC_REG_ADDR_SYSOC_BUS_TOP, CONFIG_SOC_REG_ADDR_SYSOC_SCP_TOP, \ 163 } 164 165 #define CONFIG_SOC_INIT_SYSOC_RESET_INFOS \ 166 { \ 167 /* BUS */ UINT32_C(0xf), /* SCP */ UINT32_C(0x1f), \ 168 } 169 170 #define CONFIG_SCB_ARM_TF_BASE_ADDR UINT32_C(0xA8180000) 171 #define CONFIG_SCB_ARM_TF_OFFSET (CONFIG_SCB_ARM_TF_BASE_ADDR - \ 172 HSSPI_MEM_BASE) 173 #define CONFIG_SCB_UEFI_BASE_ADDR UINT32_C(0xA8200000) 174 175 /* FWU and platform metadata address */ 176 #define CONFIG_SCB_FWU_METADATA_OFFS UINT32_C(0x500000) 177 #define CONFIG_SCB_PLAT_METADATA_OFFS UINT32_C(0x510000) 178 #define CONFIG_SCB_FWU_BANK_SIZE UINT32_C(0x400000) 179 #define CONFIG_FWU_NUM_IMAGES_PER_BANK 1 180 #define CONFIG_FWU_NUM_BANKS 2 181 #define CONFIG_FWU_MAX_COUNT 3 182 183 /* TBBR supported new FIP image offset */ 184 #define CONFIG_SCB_ARM_BL2_OFFSET UINT32_C(0x600000) 185 186 #define CONFIG_SCB_ARM_TB_BL1_BASE_ADDR UINT32_C(0xA4000000) 187 #define CONFIG_SCB_ARM_TB_BL2_BASE_ADDR UINT32_C(0xA4013000) 188 #define CONFIG_SCB_ARM_TB_BL3_BASE_ADDR UINT32_C(0xA401F000) 189 #define CONFIG_SCB_ARM_TB_BL32_BASE_ADDR UINT32_C(0xFC000000) 190 191 #define CONFIG_SCB_UART_RECV_BUF_BASE_ADDR UINT32_C(0xA4050000) 192 193 /* 125MHz / 4 = 31.25MHz */ 194 #define CONFIG_SOC_HSSPI_CLK_CONFIG \ 195 { \ 196 .clk_sel = HSSPI_EN_MCTRL_CDSS_iHCLK, .clk_div = 4, \ 197 .syncon = HSSPI_EN_MCTRL_SYNCON_SYNC \ 198 } 199 200 #define CONFIG_SOC_LPCM_SCB_TOP_ADDR UINT32_C(0x48318000) 201 #define CONFIG_SOC_LPCM_PCIE_TOP_ADDR UINT32_C(0x48319000) 202 #define CONFIG_SOC_LPCM_DMAB_TOP_ADDR UINT32_C(0x4831A000) 203 #define CONFIG_SOC_LPCM_EMMC_TOP_ADDR UINT32_C(0x48328000) 204 205 #define CONFIG_SOC_LPCM_SCB_RESET_FLAG UINT32_C(0x1) 206 #define CONFIG_SOC_LPCM_PCIE_RESET_FLAG UINT32_C(0x73) 207 #define CONFIG_SOC_LPCM_DMAB_RESET_FLAG UINT32_C(0x3) 208 209 #define CONFIG_SOC_REG_ADDR_SYS_OVER_REG_TOP UINT32_C(0x7FFF0000) 210 #define CONFIG_SOC_SYS_OVER_OFFSET_SEC_OVERRIDE UINT32_C(0x100) 211 212 #define CONFIG_SCB_DDR_FREQ DDR_FREQ_2133 213 214 #define CONFIG_SCB_USE_4BYTE_MODE 215 216 #define CONFIG_SCB_SMMU_PAGE_TABLE_BASE_ADDR UINT32_C(0xA4040000) 217 218 #define CONFIG_SOC_NORTH_SMMU_REG_BASE UINT32_C(0x78280000) 219 #define CONFIG_SOC_SOUTH_SMMU_REG_BASE UINT32_C(0x782C0000) 220 #define CONFIG_SOC_DMAB_SMMU_REG_BASE UINT32_C(0x7fb00000) 221 222 #define CONFIG_SOC_SD_CTL_REG_BASE UINT32_C(0x722E0000) 223 224 #define CONFIG_SOC_DMA330_REG_BASE UINT32_C(0x7fa00000) 225 #define CONFIG_SOC_DMAB_WRAPPER_REG UINT32_C(0x7fb80000) 226 227 #define CONFIG_SCB_ALL_OFF_LOG_GROUP UINT32_C(0x00) 228 229 /** Number of PCIe instances */ 230 #define CONFIG_SOC_PCIE_NUM 2 231 232 /* cpl timeout range value 6: 65msec ~ 210msec */ 233 #define CONFIG_SCB_PCIE_CPL_TIMEOUT_RANVE_VALUE 0x6U 234 235 /* Overriding BE[7:1] in PCIe TLP */ 236 #define CONFIG_SCB_TWEAK_PCIE_TLP_BE_OVERRIDE 0x7U 237 238 #define CONFIG_SOC_PCIE_BAR0_MASK_DEFAULT 0x0000000FFFFFFFFFLLU 239 240 #define CONFIG_SOC_PCIE_PME_SUPPORT (0x1BU) 241 #define CONFIG_SOC_PCIE_D2_SUPPORT (1U) 242 #define CONFIG_SOC_PCIE_D1_SUPPORT (1U) 243 #define CONFIG_SOC_PCIE_AUX_CURRENT (7U) 244 #define CONFIG_SOC_PCIE_DSI (0) 245 #define CONFIG_SOC_PCIE_ASPM_SUPPORT (0x3U) 246 247 #define CONFIG_SOC_PRMUX_BASE_ADDR UINT32_C(0x74600000) 248 #define CONFIG_SOC_AP_GPIO_BASE (0x71000000) 249 250 /** 251 * PRMUX settings 252 * 1:GPIO_NS 253 */ 254 #define CONFIG_SCB_PRMUX_PINGRP \ 255 { \ 256 1, 1, 1, 1, 1, 1 \ 257 } 258 259 /** 260 * GPIO direction settings 261 * 1: out 262 * 0: in 263 */ 264 #ifndef CONFIG_SCB_GPIO_DIRECTION 265 #define CONFIG_SCB_GPIO_DIRECTION \ 266 { \ 267 0, 0, 0, 0 \ 268 } 269 #endif /* CONFIG_SCB_GPIO_DIRECTION */ 270 271 /** 272 * GPIO function settings 273 * 0: GPIO 274 */ 275 #ifndef CONFIG_SCB_GPIO_FUNCTION 276 #define CONFIG_SCB_GPIO_FUNCTION \ 277 { \ 278 0, 0, 0, 0 \ 279 } 280 #endif /* CONFIG_SCB_GPIO_FUNCTION */ 281 282 #define CONFIG_SOC_I2C_ENABLE_BITMAP (1 << 0) 283 #define CONFIG_SOC_I2C_BASE_ADDRS \ 284 { \ 285 0x4A000000 \ 286 } 287 #define CONFIG_SOC_I2C_TYPES \ 288 { \ 289 I2C_TYPE_F_I2C \ 290 } 291 #define CONFIG_SOC_I2C_CHANNELS \ 292 { \ 293 I2C_EN_CH0 \ 294 } 295 296 #define CONFIG_SCB_I2C_PARAMS \ 297 { \ 298 { .I2C_PARAM_F_I2C = { .FSR_FS = 0x02, \ 299 .CSR_CS = 0x03, \ 300 .CCR_CS = 0x07, \ 301 .CCR_FM = 0x01 } }, \ 302 } 303 304 /* SRAM for one way CM3->AP mailbox for BMC bootflag */ 305 #define CONFIG_SCB_BMC_BOOTFLAG_ADDR UINT32_C(0xCE00FFF8) 306 307 #ifdef CONFIG_SCB_DIST_FIRM 308 #define CONFIG_SCB_MANUAL_THERMAL_READ 309 #endif /* CONFIG_SCB_DIST_FIRM */ 310 311 #define CONFIG_SOC_PRMUX_MAX_IDX 7 312 313 #endif /* SYNQUACER_MMAP_H */ 314