Home
last modified time | relevance | path

Searched refs:DDR_PHY1_BASE (Results 1 – 2 of 2) sorted by relevance

/SCP-firmware-master/product/juno/scp_ramfw/
A Dconfig_juno_ddr_phy400.c32 .ddr_phy_ptm = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_PTM_REGS),
33 .ddr_phy_c3a = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_C3A_REGS),
34 .ddr_phy_bl0 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL0_REGS),
35 .ddr_phy_bl1 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL1_REGS),
36 .ddr_phy_bl2 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL2_REGS),
37 .ddr_phy_bl3 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL3_REGS),
/SCP-firmware-master/product/juno/include/
A Djuno_mmap.h37 #define DDR_PHY1_BASE (EXTERNAL_RAM_BASE + 0x3FEE0000) macro

Completed in 2 milliseconds