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Searched refs:DIV (Results 1 – 25 of 25) sorted by relevance

/SCP-firmware-master/product/tc1/scp_romfw/
A Dconfig_pik_clock.c42 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV,
56 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV,
70 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV,
84 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV,
/SCP-firmware-master/product/tc2/scp_romfw/
A Dconfig_pik_clock.c42 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV,
55 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV,
68 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV,
81 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV,
/SCP-firmware-master/product/sgm776/scp_ramfw/
A Dconfig_pik_clock.c97 .divext_reg = &PIK_CLUS0->CORECLK[0].DIV,
109 .divext_reg = &PIK_CLUS0->CORECLK[1].DIV,
121 .divext_reg = &PIK_CLUS0->CORECLK[2].DIV,
133 .divext_reg = &PIK_CLUS0->CORECLK[3].DIV,
145 .divext_reg = &PIK_CLUS0->CORECLK[4].DIV,
157 .divext_reg = &PIK_CLUS0->CORECLK[5].DIV,
169 .divext_reg = &PIK_CLUS0->CORECLK[6].DIV,
181 .divext_reg = &PIK_CLUS0->CORECLK[7].DIV,
/SCP-firmware-master/product/tc0/scp_ramfw/
A Dconfig_pik_clock.c104 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV,
116 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].DIV,
128 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].DIV,
140 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].DIV,
152 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[4].DIV,
164 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[5].DIV,
176 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[6].DIV,
188 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[7].DIV,
/SCP-firmware-master/product/tc1/scp_ramfw/
A Dconfig_pik_clock.c105 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV,
117 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV,
129 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV,
141 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV,
153 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[4].DIV,
165 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[5].DIV,
177 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[6].DIV,
189 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[7].DIV,
/SCP-firmware-master/product/tc2/scp_ramfw/
A Dconfig_pik_clock.c105 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[0].DIV,
117 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[1].DIV,
129 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[2].DIV,
141 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[3].DIV,
153 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[4].DIV,
165 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[5].DIV,
177 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[6].DIV,
189 .divext_reg = &CLUSTER_PIK_PTR->CORECLK[7].DIV,
/SCP-firmware-master/product/sgi575/scp_ramfw/
A Dconfig_pik_clock.c119 .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
131 .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
143 .divext_reg = &PIK_CLUSTER(0)->CORECLK[2].DIV,
155 .divext_reg = &PIK_CLUSTER(0)->CORECLK[3].DIV,
167 .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
179 .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,
191 .divext_reg = &PIK_CLUSTER(1)->CORECLK[2].DIV,
203 .divext_reg = &PIK_CLUSTER(1)->CORECLK[3].DIV,
/SCP-firmware-master/product/rdn1e1/scp_ramfw/
A Dconfig_pik_clock.c119 .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
131 .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
143 .divext_reg = &PIK_CLUSTER(0)->CORECLK[2].DIV,
155 .divext_reg = &PIK_CLUSTER(0)->CORECLK[3].DIV,
167 .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
179 .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,
191 .divext_reg = &PIK_CLUSTER(1)->CORECLK[2].DIV,
203 .divext_reg = &PIK_CLUSTER(1)->CORECLK[3].DIV,
/SCP-firmware-master/product/sgm776/scp_romfw/
A Dconfig_pik_clock.c181 .divext_reg = &PIK_CLUS0->CORECLK[0].DIV,
193 .divext_reg = &PIK_CLUS0->CORECLK[1].DIV,
205 .divext_reg = &PIK_CLUS0->CORECLK[2].DIV,
217 .divext_reg = &PIK_CLUS0->CORECLK[3].DIV,
229 .divext_reg = &PIK_CLUS0->CORECLK[4].DIV,
241 .divext_reg = &PIK_CLUS0->CORECLK[5].DIV,
253 .divext_reg = &PIK_CLUS0->CORECLK[6].DIV,
265 .divext_reg = &PIK_CLUS0->CORECLK[7].DIV,
/SCP-firmware-master/product/tc0/scp_romfw/
A Dconfig_pik_clock.c76 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV,
89 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].DIV,
102 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].DIV,
115 .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].DIV,
/SCP-firmware-master/product/tc0/include/
A Dcpu_pik.h31 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/tc1/include/
A Dcpu_pik.h33 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/tc2/include/
A Dcpu_pik.h33 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/morello/include/
A Dmorello_pik_cpu.h32 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/n1sdp/include/
A Dn1sdp_pik_cpu.h32 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/rdv1/include/
A Dcpu_pik.h32 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/rdv1mc/include/
A Dcpu_pik.h32 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/sgi575/include/
A Dsgi575_pik_cpu.h30 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/rdn1e1/include/
A Drdn1e1_pik_cpu.h30 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/sgm776/include/
A Dsgm776_pik_cpu.h32 FWK_RW uint32_t DIV; member
/SCP-firmware-master/product/rdv1mc/scp_ramfw/
A Dconfig_pik_clock.c29 .divext_reg = &CLUSTER_PIK_PTR(n)->CORECLK[0].DIV, \
/SCP-firmware-master/product/rdv1/scp_ramfw/
A Dconfig_pik_clock.c29 .divext_reg = &CLUSTER_PIK_PTR(n)->CORECLK[0].DIV, \
/SCP-firmware-master/product/morello/scp_ramfw_fvp/
A Dconfig_pik_clock.c618 .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
631 .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
644 .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
657 .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,
/SCP-firmware-master/product/morello/scp_ramfw_soc/
A Dconfig_pik_clock.c632 .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
645 .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
658 .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
671 .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,
/SCP-firmware-master/product/n1sdp/scp_ramfw/
A Dconfig_pik_clock.c619 .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
632 .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
645 .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
658 .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,

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