1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef F_UART3_H
9 #define F_UART3_H
10 
11 #include <fwk_macros.h>
12 
13 #include <stdint.h>
14 
15 /* Normal mode registers */
16 struct f_uart3_reg {
17     FWK_RW uint32_t RFR_TFR; /* R->RFR, W->TFR */
18     FWK_RW uint32_t IER;
19     FWK_RW uint32_t IIR_FCR; /* R->IIR, W->FCR */
20     FWK_RW uint32_t LCR;
21     FWK_RW uint32_t MCR;
22     FWK_R uint32_t LSR;
23     FWK_R uint32_t MSR;
24     FWK_RW uint32_t SCR;
25 };
26 
27 /* DivLatch access registers */
28 struct f_uart3_dla_reg {
29     FWK_RW uint32_t DLL;
30     FWK_RW uint32_t DLM;
31     FWK_RW uint32_t IIR_FCR; /* R->IIR, W->FCR */
32     FWK_RW uint32_t LCR;
33     FWK_RW uint32_t MCR;
34     FWK_R uint32_t LSR;
35     FWK_R uint32_t MSR;
36     FWK_W uint32_t TST;
37 };
38 
39 /* Bit definition */
40 /* Interrupt Enable Register */
41 #define F_UART3_IER_ERBFI ((uint32_t)(0x1 << 0))
42 #define F_UART3_IER_ETBEI ((uint32_t)(0x1 << 1))
43 #define F_UART3_IER_ELSI ((uint32_t)(0x1 << 2))
44 #define F_UART3_IER_EDSSI ((uint32_t)(0x1 << 3))
45 
46 /* Interrupt Identification Register */
47 #define F_UART3_IIR_ID ((uint32_t)(0xF << 0))
48 #define F_UART3_IIR_FIFO ((uint32_t)(0x3 << 6))
49 #define F_UART3_IIR_ID_NOINTR (uint32_t(0x1))
50 #define F_UART3_IIR_ID_RLINE (uint32_t(0x6))
51 #define F_UART3_IIR_ID_RDATA (uint32_t(0x4))
52 #define F_UART3_IIR_ID_TIMEOUT (uint32_t(0xC))
53 #define F_UART3_IIR_ID_TFEMPTY (uint32_t(0x2))
54 #define F_UART3_IIR_ID_MODEM (uint32_t(0x0))
55 
56 /* FIFO Control Register */
57 #define F_UART3_FCR_RXFRST ((uint32_t)(0x1 << 1))
58 #define F_UART3_FCR_TXFRST ((uint32_t)(0x1 << 2))
59 #define F_UART3_FCR_DMA ((uint32_t)(0x1 << 3))
60 #define F_UART3_FCR_RCVR ((uint32_t)(0x3 << 6))
61 
62 /* Rx FIFO trigger level */
63 #define F_UART3_FCR_RCVR_1B ((uint32_t)(0x0 << 6))
64 #define F_UART3_FCR_RCVR_4B ((uint32_t)(0x1 << 6))
65 #define F_UART3_FCR_RCVR_8B ((uint32_t)(0x2 << 6))
66 #define F_UART3_FCR_RCVR_14B ((uint32_t)(0x3 << 6))
67 
68 /* Line Control Register */
69 #define F_UART3_LCR_WLS ((uint32_t)(0x3 << 0))
70 #define F_UART3_LCR_STB ((uint32_t)(0x3 << 2))
71 #define F_UART3_LCR_PEN ((uint32_t)(0x1 << 3))
72 #define F_UART3_LCR_EPS ((uint32_t)(0x1 << 4))
73 #define F_UART3_LCR_SP ((uint32_t)(0x1 << 5))
74 #define F_UART3_LCR_SB ((uint32_t)(0x1 << 6))
75 #define F_UART3_LCR_DLAB ((uint32_t)(0x1 << 7))
76 /* Word length */
77 #define F_UART3_LCR_WLS_5 ((uint32_t)(0x0))
78 #define F_UART3_LCR_WLS_6 ((uint32_t)(0x1))
79 #define F_UART3_LCR_WLS_7 ((uint32_t)(0x2))
80 #define F_UART3_LCR_WLS_8 ((uint32_t)(0x3))
81 
82 /* Modem Control Register */
83 #define F_UART3_MCR_DTR ((uint32_t)(0x1 << 0))
84 #define F_UART3_MCR_RTS ((uint32_t)(0x1 << 1))
85 #define F_UART3_MCR_OUT1 ((uint32_t)(0x1 << 2))
86 #define F_UART3_MCR_OUT2 ((uint32_t)(0x1 << 3))
87 #define F_UART3_MCR_LOOP ((uint32_t)(0x1 << 4))
88 
89 /* Line Status Register */
90 #define F_UART3_LSR_DR ((uint32_t)(0x1 << 0))
91 #define F_UART3_LSR_OE ((uint32_t)(0x1 << 1))
92 #define F_UART3_LSR_PE ((uint32_t)(0x1 << 2))
93 #define F_UART3_LSR_FE ((uint32_t)(0x1 << 3))
94 #define F_UART3_LSR_BI ((uint32_t)(0x1 << 4))
95 #define F_UART3_LSR_THRE ((uint32_t)(0x1 << 5))
96 #define F_UART3_LSR_TEMT ((uint32_t)(0x1 << 6))
97 #define F_UART3_LSR_ERRF ((uint32_t)(0x1 << 7))
98 
99 /* Modem Status Register */
100 #define F_UART3_MSR_DCTS ((uint32_t)(0x1 << 0))
101 #define F_UART3_MSR_DDSR ((uint32_t)(0x1 << 1))
102 #define F_UART3_MSR_TERI ((uint32_t)(0x1 << 2))
103 #define F_UART3_MSR_DDCD ((uint32_t)(0x1 << 3))
104 #define F_UART3_MSR_CTS ((uint32_t)(0x1 << 4))
105 #define F_UART3_MSR_DSR ((uint32_t)(0x1 << 5))
106 #define F_UART3_MSR_RI ((uint32_t)(0x1 << 6))
107 #define F_UART3_MSR_DCD ((uint32_t)(0x1 << 7))
108 
109 /*
110  * Baud rate
111  * F_UART3 Clock domain: MAIN_CRG11.CLK6
112  *            freq  : 500MHz/8 = 62.5MHz
113  *
114  * DivRatio = Freq(Hz) / (16 * BaudRate(bps))
115  */
116 
117 /* 230.4 kbps (DivRatio: 16.95) */
118 #define F_UART3_DLL_230400 ((uint32_t)(0x11))
119 #define F_UART3_DLM_230400 ((uint32_t)(0x00))
120 
121 /* 115.2 kbps (DivRatio: 33.91) */
122 #define F_UART3_DLL_115200 ((uint32_t)(0x22))
123 #define F_UART3_DLM_115200 ((uint32_t)(0x00))
124 
125 /* 57.6 kbps (DivRatio: 67.82) */
126 #define F_UART3_DLL_57600 ((uint32_t)(0x44))
127 #define F_UART3_DLM_57600 ((uint32_t)(0x00))
128 
129 /* 38.4 kbps (DivRatio: 101.73) */
130 #define F_UART3_DLL_38400 ((uint32_t)(0x66))
131 #define F_UART3_DLM_38400 ((uint32_t)(0x00))
132 
133 /* 19.2 kbps (DivRatio: 203.45) */
134 #define F_UART3_DLL_19200 ((uint32_t)(0xCC))
135 #define F_UART3_DLM_19200 ((uint32_t)(0x00))
136 
137 /* 9.6 kbps (DivRatio: 409.9) */
138 #define F_UART3_DLL_9600 ((uint32_t)(0x9A))
139 #define F_UART3_DLM_9600 ((uint32_t)(0x01))
140 
141 #define F_UART3_SYSPARAM_BAUD_RATE_9600 (0)
142 #define F_UART3_SYSPARAM_BAUD_RATE_19200 (1)
143 #define F_UART3_SYSPARAM_BAUD_RATE_38400 (2)
144 #define F_UART3_SYSPARAM_BAUD_RATE_57600 (3)
145 #define F_UART3_SYSPARAM_BAUD_RATE_115200 (4)
146 #define F_UART3_SYSPARAM_BAUD_RATE_230400 (5)
147 #define F_UART3_SYSPARAM_BAUD_RATE_MAX (5)
148 
149 typedef enum {
150     F_UART3_NEWLINE_CODE_CRLF = 0,
151     F_UART3_NEWLINE_CODE_CR = 1,
152     F_UART3_NEWLINE_CODE_LF = 2
153 } F_UART3_newline_code_t;
154 
155 #endif /* F_UART3_H */
156