1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Cadence I2C register definitions 9 */ 10 11 #ifndef INTERNAL_CDNS_I2C_H 12 #define INTERNAL_CDNS_I2C_H 13 14 #include <fwk_macros.h> 15 16 #include <stdint.h> 17 18 struct cdns_i2c_reg { 19 /* Control Register */ 20 FWK_RW uint16_t CR; 21 uint8_t RESERVED0[2]; 22 /* Status Register */ 23 FWK_RW uint16_t SR; 24 uint8_t RESERVED1[2]; 25 /* Address Register */ 26 FWK_RW uint16_t AR; 27 uint8_t RESERVED2[2]; 28 /* Data Register */ 29 FWK_RW uint16_t DR; 30 uint8_t RESERVED3[2]; 31 /* Interrupt Status Register */ 32 FWK_RW uint16_t ISR; 33 uint8_t RESERVED4[2]; 34 /* Transfer Size Register */ 35 FWK_RW uint8_t TSR; 36 uint8_t RESERVED5[3]; 37 /* Target Monitor Pause Register */ 38 FWK_RW uint8_t SMPR; 39 uint8_t RESERVED6[3]; 40 /* Timeout Register */ 41 FWK_RW uint8_t TOR; 42 uint8_t RESERVED7[3]; 43 /* Interrupt Mask Register */ 44 FWK_RW uint16_t IMR; 45 uint8_t RESERVED8[2]; 46 /* Interrupt Enable Register */ 47 FWK_RW uint16_t IER; 48 uint8_t RESERVED9[2]; 49 /* Interrupt Disable Register */ 50 FWK_RW uint16_t IDR; 51 uint8_t RESERVED10[2]; 52 /* Glitch Filter Control Register */ 53 FWK_RW uint16_t GFCR; 54 }; 55 56 /* Register Field Definitions */ 57 58 #define I2C_CR_DIV_MASK 0xFF00 59 #define I2C_CR_DIV_SHIFT 8 60 #define I2C_CR_DIV_A_MASK 0x000C 61 #define I2C_CR_DIV_A_SHIFT 14 62 #define I2C_CR_DIV_B_MASK 0x003F 63 #define I2C_CR_DIV_B_SHIFT 8 64 #define I2C_CR_CLRFIFO_MASK 0x0040 65 #define I2C_CR_CLRFIFO_SHIFT 6 66 #define I2C_CR_SLVMON_MASK 0x0020 67 #define I2C_CR_SLVMON_SHIFT 5 68 #define I2C_CR_HOLD_MASK 0x0010 69 #define I2C_CR_HOLD_SHIFT 4 70 #define I2C_CR_ACKEN_MASK 0x0008 71 #define I2C_CR_ACKEN_SHIFT 3 72 #define I2C_CR_NEA_MASK 0x0004 73 #define I2C_CR_NEA_SHIFT 2 74 #define I2C_CR_MS_MASK 0x0002 75 #define I2C_CR_MS_SHIFT 1 76 #define I2C_CR_RW_MASK 0x0001 77 #define I2C_CR_RW_SHIFT 0 78 79 #define I2C_SR_BA_MASK 0x0100 80 #define I2C_SR_BA_SHIFT 8 81 #define I2C_SR_RXOVF_MASK 0x0080 82 #define I2C_SR_RXOVF_SHIFT 7 83 #define I2C_SR_TXDV_MASK 0x0040 84 #define I2C_SR_TXDV_SHIFT 6 85 #define I2C_SR_RXDV_MASK 0x0020 86 #define I2C_SR_RXDV_SHIFT 5 87 #define I2C_SR_RXRW_MASK 0x0008 88 #define I2C_SR_RXRW_SHIFT 3 89 90 #define I2C_AR_ADD7_MASK 0x007F 91 #define I2C_AR_ADD7_SHIFT 0 92 #define I2C_AR_ADD10_MASK 0x03FF 93 #define I2C_AR_ADD10_SHIFT 0 94 95 #define I2C_DR_DATA_MASK 0x00FF 96 #define I2C_DR_DATA_SHIFT 0 97 98 #define I2C_ISR_MASK 0x02FF 99 #define I2C_ISR_SHIFT 0 100 #define I2C_ISR_ARBLOST_MASK 0x0200 101 #define I2C_ISR_ARBLOST_SHIFT 9 102 #define I2C_ISR_RXUNF_MASK 0x0080 103 #define I2C_ISR_RXUNF_SHIFT 7 104 #define I2C_ISR_TXOVF_MASK 0x0040 105 #define I2C_ISR_TXOVF_SHIFT 6 106 #define I2C_ISR_RXOVF_MASK 0x0020 107 #define I2C_ISR_RXOVF_SHIFT 5 108 #define I2C_ISR_SLVRDY_MASK 0x0010 109 #define I2C_ISR_SLVRDY_SHIFT 4 110 #define I2C_ISR_TO_MASK 0x0008 111 #define I2C_ISR_TO_SHIFT 3 112 #define I2C_ISR_NACK_MASK 0x0004 113 #define I2C_ISR_NACK_SHIFT 2 114 #define I2C_ISR_DATA_MASK 0x0002 115 #define I2C_ISR_DATA_SHIFT 1 116 #define I2C_ISR_COMP_MASK 0x0001 117 #define I2C_ISR_COMP_SHIFT 0 118 119 #define I2C_TSR_SIZE_MASK 0xFF 120 #define I2C_TSR_SIZE_SHIFT 0 121 122 #define I2C_SMPR_PAUSE_MASK 0x0F 123 #define I2C_SMPR_PAUSE_SHIFT 0 124 125 #define I2C_TOR_TIMEOUT_MASK 0xFF 126 #define I2C_TOR_TIMEOUT_SHIFT 0 127 128 #define I2C_IMR_ARBLOST_MASK 0x0200 129 #define I2C_IMR_ARBLOST_SHIFT 9 130 #define I2C_IMR_RXUNF_MASK 0x0080 131 #define I2C_IMR_RXUNF_SHIFT 7 132 #define I2C_IMR_TXOVF_MASK 0x0040 133 #define I2C_IMR_TXOVF_SHIFT 6 134 #define I2C_IMR_RXOVF_MASK 0x0020 135 #define I2C_IMR_RXOVF_SHIFT 5 136 #define I2C_IMR_SLVRDY_MASK 0x0010 137 #define I2C_IMR_SLVRDY_SHIFT 4 138 #define I2C_IMR_TO_MASK 0x0008 139 #define I2C_IMR_TO_SHIFT 3 140 #define I2C_IMR_NACK_MASK 0x0004 141 #define I2C_IMR_NACK_SHIFT 2 142 #define I2C_IMR_DATA_MASK 0x0002 143 #define I2C_IMR_DATA_SHIFT 1 144 #define I2C_IMR_COMP_MASK 0x0001 145 #define I2C_IMR_COMP_SHIFT 0 146 147 #define I2C_IER_ARBLOST_MASK 0x0200 148 #define I2C_IER_ARBLOST_SHIFT 9 149 #define I2C_IER_RXUNF_MASK 0x0080 150 #define I2C_IER_RXUNF_SHIFT 7 151 #define I2C_IER_TXOVF_MASK 0x0040 152 #define I2C_IER_TXOVF_SHIFT 6 153 #define I2C_IER_RXOVF_MASK 0x0020 154 #define I2C_IER_RXOVF_SHIFT 5 155 #define I2C_IER_SLVRDY_MASK 0x0010 156 #define I2C_IER_SLVRDY_SHIFT 4 157 #define I2C_IER_TO_MASK 0x0008 158 #define I2C_IER_TO_SHIFT 3 159 #define I2C_IER_NACK_MASK 0x0004 160 #define I2C_IER_NACK_SHIFT 2 161 #define I2C_IER_DATA_MASK 0x0002 162 #define I2C_IER_DATA_SHIFT 1 163 #define I2C_IER_COMP_MASK 0x0001 164 #define I2C_IER_COMP_SHIFT 0 165 166 #define I2C_IDR_ARBLOST_MASK 0x0200 167 #define I2C_IDR_ARBLOST_SHIFT 9 168 #define I2C_IDR_RXUNF_MASK 0x0080 169 #define I2C_IDR_RXUNF_SHIFT 7 170 #define I2C_IDR_TXOVF_MASK 0x0040 171 #define I2C_IDR_TXOVF_SHIFT 6 172 #define I2C_IDR_RXOVF_MASK 0x0020 173 #define I2C_IDR_RXOVF_SHIFT 5 174 #define I2C_IDR_SLVRDY_MASK 0x0010 175 #define I2C_IDR_SLVRDY_SHIFT 4 176 #define I2C_IDR_TO_MASK 0x0008 177 #define I2C_IDR_TO_SHIFT 3 178 #define I2C_IDR_NACK_MASK 0x0004 179 #define I2C_IDR_NACK_SHIFT 2 180 #define I2C_IDR_DATA_MASK 0x0002 181 #define I2C_IDR_DATA_SHIFT 1 182 #define I2C_IDR_COMP_MASK 0x0001 183 #define I2C_IDR_COMP_SHIFT 0 184 185 #define I2C_GFCR_DEPTH_MASK 0xFFFF 186 #define I2C_GFCR_DEPTH_SHIFT 0 187 188 /* I2C Driver Macros */ 189 190 #define I2C_RW_WRITE 0 191 #define I2C_RW_READ 1 192 193 #define I2C_MS_TARGET 0 194 #define I2C_MS_CONTROLLER 1 195 196 #define I2C_NEA_10BIT 0 197 #define I2C_NEA_7BIT 1 198 199 #define I2C_ACKEN_OFF 0 200 #define I2C_ACKEN_ON 1 201 202 #define I2C_HOLD_OFF 0 203 #define I2C_HOLD_ON 1 204 205 #define I2C_CLRFIFO_OFF 0 206 #define I2C_CLRFIFO_ON 1 207 208 #define I2C_TOR_TIMEOUT_VALUE 0xFF 209 210 #endif /* INTERNAL_CDNS_I2C_H */ 211