1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef INTERNAL_MHU3_H 9 #define INTERNAL_MHU3_H 10 11 #include <mod_mhu3.h> 12 13 #include <fwk_macros.h> 14 15 #include <stdint.h> 16 17 #define MHU3_MAX_DOORBELL_CHANNELS UINT32_C(128) 18 19 /* 20 * Useful macros 21 */ 22 #define MHU3_MASK_GENERATE(BITSTART, LENGTH) \ 23 (((1 << (LENGTH)) - 1) << ((BITSTART) + 1 - (LENGTH))) 24 #define MHU3_MASKED_RECOVER(MASKED, BITSTART, LENGTH) \ 25 ((MASKED) >> ((BITSTART) + 1 - (LENGTH))) 26 27 /* 28 * Top level base addresses 29 */ 30 #define MHU3_PBX_PDBCW_PAGE_OFFSET UINT32_C(0x00001000) 31 #define MHU3_PBX_PFCW_PAGE_OFFSET UINT32_C(0x00003000) 32 33 #define MHU3_MBX_MDBCW_PAGE_OFFSET UINT32_C(0x00001000) 34 #define MHU3_MBX_MDFCW_PAGE_OFFSET UINT32_C(0x00003000) 35 36 #define FCH_WS_64BIT 64U 37 #define FCH_WS_32BIT 32U 38 39 enum mhu3_reg_settings { 40 MHU3_OP_REQ = 1U << 0U, 41 MHU3_AUTO_OP_SPT = 1U << 0U, 42 }; 43 44 /*! 45 * \brief MHU3 Postbox(PBX) Register Definitions 46 */ 47 48 struct mhu3_pbx_reg { 49 /*! Postbox control page */ 50 FWK_R uint32_t MHU_BLK_ID; 51 uint8_t RESERVED1[0x10 - 0x04]; 52 FWK_R uint32_t PBX_FEAT_SPT0; 53 FWK_R uint32_t PBX_FEAT_SPT1; 54 uint8_t RESERVED2[0x20 - 0x18]; 55 FWK_R uint32_t PBX_DBCH_CFG0; 56 uint8_t RESERVED3[0x30 - 0x24]; 57 FWK_R uint32_t PBX_FFCH_CFG0; 58 uint8_t RESERVED4[0x40 - 0x34]; 59 FWK_R uint32_t PBX_FCH_CFG0; 60 uint8_t RESERVED5[0x50 - 0x44]; 61 FWK_R uint32_t PBX_DCH_CFG0; 62 uint8_t RESERVED6[0x100 - 0x54]; 63 FWK_RW uint32_t PBX_CTRL; 64 uint8_t RESERVED7[0x150 - 0x104]; 65 FWK_RW uint32_t PBX_DMA_CTRL; 66 FWK_R uint32_t PBX_DMA_ST; 67 FWK_RW uint64_t PBX_DMA_CDL_BASE; 68 FWK_RW uint32_t PBX_DMA_CDL_PROP; 69 uint8_t RESERVED8[0x400 - 0x164]; 70 FWK_R uint32_t PBX_DBCH_INT_ST[(0x410 - 0x400) >> 2]; 71 FWK_R uint32_t PBX_FFCH_INT_ST[(0x430 - 0x410) >> 2]; 72 FWK_R uint32_t PBX_DCH_INT_ST; 73 uint8_t RESERVED9[0xFC8 - 0x434]; 74 FWK_R uint32_t IIDR; 75 FWK_R uint32_t AIDR; 76 FWK_R uint32_t IMPL_DEF_ID[4 * 11]; 77 }; 78 79 struct mhu3_pbx_pdbcw_reg { 80 FWK_R uint32_t PDBCW_ST; 81 uint8_t RESERVED1[0xC - 0x4]; 82 FWK_W uint32_t PDBCW_SET; 83 FWK_R uint32_t PDBCW_INT_ST; 84 FWK_W uint32_t PDBCW_INT_CLR; 85 FWK_RW uint32_t PDBCW_INT_EN; 86 FWK_RW uint32_t PDBCW_CTRL; 87 }; 88 89 struct mhu3_mbx_reg { 90 /*! Mailbox control page */ 91 FWK_R uint32_t MHU_BLK_ID; 92 uint8_t RESERVED1[0x10 - 0x04]; 93 FWK_R uint32_t MBX_FEAT_SPT0; 94 FWK_R uint32_t MBX_FEAT_SPT1; 95 uint8_t RESERVED2[0x20 - 0x18]; 96 FWK_R uint32_t MBX_DBCH_CFG0; 97 uint8_t RESERVED3[0x30 - 0x24]; 98 FWK_R uint32_t MBX_FFCH_CFG0; 99 uint8_t RESERVED4[0x40 - 0x34]; 100 FWK_R uint32_t MBX_FCH_CFG0; 101 uint8_t RESERVED5[0x50 - 0x44]; 102 FWK_R uint32_t MBX_DCH_CFG0; 103 uint8_t RESERVED6[0x100 - 0x54]; 104 FWK_RW uint32_t MBX_CTRL; 105 uint8_t RESERVED7[0x140 - 0x104]; 106 FWK_RW uint32_t MBX_FCH_CTRL; 107 FWK_RW uint32_t MBX_FCG_INT_EN; 108 uint8_t RESERVED8[0x150 - 0x148]; 109 FWK_RW uint32_t MBX_DMA_CTRL; 110 FWK_R uint32_t MBX_DMA_ST; 111 FWK_RW uint64_t MBX_DMA_CDL_BASE; 112 FWK_RW uint32_t MBX_DMA_CDL_PROP; 113 uint8_t RESERVED9[0x400 - 0x164]; 114 FWK_R uint32_t MBX_DBCH_INT_ST[(0x410 - 0x400) >> 2]; 115 FWK_R uint32_t MBX_FFCH_INT_ST[(0x420 - 0x410) >> 2]; 116 FWK_R uint32_t MBX_FCG_INT_ST; 117 uint8_t RESERVED10[0x430 - 0x424]; 118 FWK_R uint32_t MBX_FCH_GRP_INT_ST[(0x4B0 - 0x430) >> 2]; 119 FWK_R uint32_t MBX_DCH_INT_ST; 120 uint8_t RESERVED11[0xFC8 - 0x4B4]; 121 FWK_R uint32_t IIDR; 122 FWK_R uint32_t AIDR; 123 FWK_R uint32_t IMPL_DEF_ID[4 * 11]; 124 }; 125 126 struct mhu3_mbx_mdbcw_reg { 127 FWK_R uint32_t MDBCW_ST; 128 FWK_R uint32_t MDBCW_ST_MSK; 129 FWK_RW uint32_t MDBCW_CLR; 130 uint8_t RESERVED1[0x10 - 0x0C]; 131 FWK_R uint32_t MDBCW_MSK_ST; 132 FWK_RW uint32_t MDBCW_MSK_SET; 133 FWK_RW uint32_t MDBCW_MSK_CLR; 134 FWK_RW uint32_t MDBCW_CTRL; 135 }; 136 137 /* Fast Channel Configuration 0 Number of Fast Channels Start Bit */ 138 #define MHU3_FCH_CFG0_NUM_FCH_BITSTART 9 139 /* Fast Channel Configuration 0 Number of Fast Channels Length */ 140 #define MHU3_FCH_CFG0_NUM_FCH_LEN 10 141 /* Fast Channel Configuration 0 Number of Fast Channels Mask */ 142 #define MHU3_FCH_CFG0_NUM_FCH_MASK \ 143 (MHU3_MASK_GENERATE( \ 144 MHU3_FCH_CFG0_NUM_FCH_BITSTART, MHU3_FCH_CFG0_NUM_FCH_LEN)) 145 146 /* Fast Channel Configuration 0 Number of Fast Channel Groups Start Bit */ 147 #define MHU3_FCH_CFG0_NUM_FCG_BITSTART 15 148 /* Fast Channel Configuration 0 Number of Fast Channel Groups Length */ 149 #define MHU3_FCH_CFG0_NUM_FCG_LEN 5 150 /* Fast Channel Configuration 0 Number of Fast Channel Groups Mask */ 151 #define MHU3_FCH_CFG0_NUM_FCG_MASK \ 152 (MHU3_MASK_GENERATE( \ 153 MHU3_FCH_CFG0_NUM_FCG_BITSTART, MHU3_FCH_CFG0_NUM_FCG_LEN)) 154 155 /* 156 * Fast Channel Configuration 0 Number of Fast Channels per Fast Channel Group 157 * Start Bit 158 */ 159 #define MHU3_FCH_CFG0_NUM_FCH_PER_GRP_BITSTART 20 160 /* 161 * Fast Channel Configuration 0 Number of Fast Channels per Fast Channel Group 162 * Length 163 */ 164 #define MHU3_FCH_CFG0_NUM_FCH_PER_GRP_LEN 5 165 /* 166 * Fast Channel Configuration 0 Number of Fast Channels per Fast Channel Group 167 * Mask 168 */ 169 #define MHU3_FCH_CFG0_NUM_FCH_PER_GRP_MASK \ 170 (MHU3_MASK_GENERATE( \ 171 MHU3_FCH_CFG0_NUM_FCH_PER_GRP_BITSTART, \ 172 MHU3_FCH_CFG0_NUM_FCH_PER_GRP_LEN)) 173 174 /* Fast Channel Configuration 0 Fast Channel Word Size Start Bit */ 175 #define MHU3_FCH_CFG0_FCH_WS_BITSTART 28 176 /* Fast Channel Configuration 0 Fast Channel Word Size Length */ 177 #define MHU3_FCH_CFG0_FCH_WS_LEN 8 178 /* Fast Channel Configuration 0 Fast Channel Word Size Mask */ 179 #define MHU3_FCH_CFG0_FCH_WS_MASK \ 180 (MHU3_MASK_GENERATE( \ 181 MHU3_FCH_CFG0_FCH_WS_BITSTART, MHU3_FCH_CFG0_FCH_WS_LEN)) 182 183 /* Feature Support 0 Doorbell Extension Support Start Bit */ 184 #define MHU3_FEAT_SPT0_DBE_SPT_BITSTART 3 185 /* Feature Support 0 Doorbell Extension Support Length */ 186 #define MHU3_FEAT_SPT0_DBE_SPT_LEN 4 187 /* Feature Support 0 Doorbell Extension Support Mask */ 188 #define MHU3_FEAT_SPT0_DBE_SPT_MASK \ 189 (MHU3_MASK_GENERATE( \ 190 MHU3_FEAT_SPT0_DBE_SPT_BITSTART, MHU3_FEAT_SPT0_DBE_SPT_LEN)) 191 192 /* Feature Support 0 FIFO Extension Support Start Bit */ 193 #define MHU3_FEAT_SPT0_FE_SPT_BITSTART 7 194 /* Feature Support 0 FIFO Extension Support Length */ 195 #define MHU3_FEAT_SPT0_FE_SPT_LEN 4 196 /* Feature Support 0 FIFO Extension Support Mask */ 197 #define MHU3_FEAT_SPT0_FE_SPT_MASK \ 198 (MHU3_MASK_GENERATE( \ 199 MHU3_FEAT_SPT0_FE_SPT_BITSTART, MHU3_FEAT_SPT0_FE_SPT_LEN)) 200 201 /* Feature Support 0 Fast Channel Extension Support Start Bit */ 202 #define MHU3_FEAT_SPT0_FCE_SPT_BITSTART 11 203 /* Feature Support 0 Fast Channel Extension Support Length */ 204 #define MHU3_FEAT_SPT0_FCE_SPT_LEN 4 205 /* Feature Support 0 Fast Channel Extension Support Mask */ 206 #define MHU3_FEAT_SPT0_FCE_SPT_MASK \ 207 (MHU3_MASK_GENERATE( \ 208 MHU3_FEAT_SPT0_FCE_SPT_BITSTART, MHU3_FEAT_SPT0_FCE_SPT_LEN)) 209 210 /* Feature Support 0 TrustZone Extension Support Start Bit */ 211 #define MHU3_FEAT_SPT0_TZE_SPT_BITSTART 15 212 /* Feature Support 0 TrustZone Extension Support Length */ 213 #define MHU3_FEAT_SPT0_TZE_SPT_LEN 4 214 /* Feature Support 0 TrustZone Extension Support Mask */ 215 #define MHU3_FEAT_SPT0_TZE_SPT_MASK \ 216 (MHU3_MASK_GENERATE( \ 217 MHU3_FEAT_SPT0_TZE_SPT_BITSTART, MHU3_FEAT_SPT0_TZE_SPT_LEN)) 218 219 /* Feature Support 0 Realm Management Extension Support Start Bit */ 220 #define MHU3_FEAT_SPT0_RME_SPT_BITSTART 19 221 /* Feature Support 0 Realm Management Extension Support Length */ 222 #define MHU3_FEAT_SPT0_RME_SPT_LEN 4 223 /* Feature Support 0 Realm Management Extension Support Mask */ 224 #define MHU3_FEAT_SPT0_RME_SPT_MASK \ 225 (MHU3_MASK_GENERATE( \ 226 MHU3_FEAT_SPT0_RME_SPT_BITSTART, MHU3_FEAT_SPT0_RME_SPT_LEN)) 227 228 #endif /* INTERNAL_MHU3_H */ 229