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Searched refs:MR5 (Results 1 – 2 of 2) sorted by relevance

/SCP-firmware-master/product/synquacer/module/synquacer_memc/src/
A Dddr_init.c678 REG_DDRPHY_CONFIG->MR5 = 0x00000500; in ddr_init_phy0_mp()
944 REG_DDRPHY_CONFIG->MR5 = (REG_DDRPHY_CONFIG->MR5 & 0xFFFFE3FF) | 0x00001800; in ddr_init_phy0_mp()
954 REG_DDRPHY_CONFIG->MR5 = (REG_DDRPHY_CONFIG->MR5 & 0xFFFFFFF8) | 0x00000001; in ddr_init_phy0_mp()
/SCP-firmware-master/product/synquacer/module/synquacer_memc/include/internal/
A Dreg_DDRPHY_CONFIG.h115 uint32_t MR5; // 0x065 member

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