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Searched refs:PIK_CLK_RATE_CLUS1_ATCLK (Results 1 – 6 of 6) sorted by relevance

/SCP-firmware-master/product/n1sdp/scp_ramfw/
A Dconfig_clock.h47 #define PIK_CLK_RATE_CLUS1_ATCLK (900 * FWK_MHZ) macro
A Dconfig_pik_clock.c257 .rate = PIK_CLK_RATE_CLUS1_ATCLK,
260 .divider = PIK_CLK_RATE_CLUS1 / PIK_CLK_RATE_CLUS1_ATCLK,
776 .initial_rate = PIK_CLK_RATE_CLUS1_ATCLK,
/SCP-firmware-master/product/morello/scp_ramfw_fvp/
A Dconfig_clock.h55 #define PIK_CLK_RATE_CLUS1_ATCLK (900 * FWK_MHZ) macro
A Dconfig_pik_clock.c256 .rate = PIK_CLK_RATE_CLUS1_ATCLK,
259 .divider = PIK_CLK_RATE_CLUS1 / PIK_CLK_RATE_CLUS1_ATCLK,
775 .initial_rate = PIK_CLK_RATE_CLUS1_ATCLK,
/SCP-firmware-master/product/morello/scp_ramfw_soc/
A Dconfig_clock.h56 #define PIK_CLK_RATE_CLUS1_ATCLK (800 * FWK_MHZ) macro
A Dconfig_pik_clock.c251 .rate = PIK_CLK_RATE_CLUS1_ATCLK,
254 .divider = PIK_CLK_RATE_CLUS1 / PIK_CLK_RATE_CLUS1_ATCLK,
789 .initial_rate = PIK_CLK_RATE_CLUS1_ATCLK,

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