Home
last modified time | relevance | path

Searched refs:PLL_REG0_NF (Results 1 – 3 of 3) sorted by relevance

/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/
A Djuno_soc_clock_ram_pll.c98 feedback_div = ((pll->REG0 & PLL_REG0_NF) >> PLL_REG0_NF_POS) + 1; in juno_soc_clock_ram_pll_get()
/SCP-firmware-master/product/juno/include/
A Djuno_scc.h46 #define PLL_REG0_NF UINT32_C(0x1FFF0000) macro
/SCP-firmware-master/product/juno/module/juno_hdlcd/src/
A Dmod_juno_hdlcd.c450 nf = ((SCC->PLL[PLL_IDX_HDLCD].REG0 & PLL_REG0_NF) >> PLL_REG0_NF_POS) + 1; in juno_hdlcd_start()

Completed in 5 milliseconds