PLL_REG0_PLL_RESET (reference) in projects: SCP-firmware-master

Searched refs:PLL_REG0_PLL_RESET (Results 1 – 5 of 5) sorted by relevance

/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/
A D	juno_soc_clock_ram_pll.c	`46 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in juno_soc_clock_ram_pll_init() 68 pll->REG0 = PLL_REG0_PLL_RESET \| in juno_soc_clock_ram_pll_set() 77 pll->REG0 &= ~PLL_REG0_PLL_RESET; in juno_soc_clock_ram_pll_set()`
/SCP-firmware-master/product/juno/scp_romfw_bypass/
A D	juno_pll_workaround.c	`36 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in __wrap_arch_exception_reset()`
/SCP-firmware-master/product/juno/module/juno_soc_clock/src/
A D	mod_juno_soc_clock.c	`81 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in pll_init()`
/SCP-firmware-master/product/juno/include/
A D	juno_scc.h	`43 #define PLL_REG0_PLL_RESET UINT32_C(0x80000000) macro`
/SCP-firmware-master/product/juno/module/juno_hdlcd/src/
A D	mod_juno_hdlcd.c	`247 SCC->PLL[PLL_IDX_HDLCD].REG0 = (PLL_REG0_PLL_RESET \| PLL_REG0_HARD_BYPASS); in juno_hdlcd_set_rate()`

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