1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CONFIG_PPU_V0_H 9 #define CONFIG_PPU_V0_H 10 11 enum ppu_v0_element_idx { 12 PPU_V0_ELEMENT_IDX_CLUSTER0_CPU0, 13 PPU_V0_ELEMENT_IDX_CLUSTER0_CPU1, 14 PPU_V0_ELEMENT_IDX_CLUSTER1_CPU0, 15 PPU_V0_ELEMENT_IDX_CLUSTER1_CPU1, 16 PPU_V0_ELEMENT_IDX_CLUSTER2_CPU0, 17 PPU_V0_ELEMENT_IDX_CLUSTER2_CPU1, 18 PPU_V0_ELEMENT_IDX_CLUSTER3_CPU0, 19 PPU_V0_ELEMENT_IDX_CLUSTER3_CPU1, 20 PPU_V0_ELEMENT_IDX_CLUSTER4_CPU0, 21 PPU_V0_ELEMENT_IDX_CLUSTER4_CPU1, 22 PPU_V0_ELEMENT_IDX_CLUSTER5_CPU0, 23 PPU_V0_ELEMENT_IDX_CLUSTER5_CPU1, 24 PPU_V0_ELEMENT_IDX_CLUSTER6_CPU0, 25 PPU_V0_ELEMENT_IDX_CLUSTER6_CPU1, 26 PPU_V0_ELEMENT_IDX_CLUSTER7_CPU0, 27 PPU_V0_ELEMENT_IDX_CLUSTER7_CPU1, 28 PPU_V0_ELEMENT_IDX_CLUSTER8_CPU0, 29 PPU_V0_ELEMENT_IDX_CLUSTER8_CPU1, 30 PPU_V0_ELEMENT_IDX_CLUSTER9_CPU0, 31 PPU_V0_ELEMENT_IDX_CLUSTER9_CPU1, 32 PPU_V0_ELEMENT_IDX_CLUSTER10_CPU0, 33 PPU_V0_ELEMENT_IDX_CLUSTER10_CPU1, 34 PPU_V0_ELEMENT_IDX_CLUSTER11_CPU0, 35 PPU_V0_ELEMENT_IDX_CLUSTER11_CPU1, 36 PPU_V0_ELEMENT_IDX_CLUSTER0, 37 PPU_V0_ELEMENT_IDX_CLUSTER1, 38 PPU_V0_ELEMENT_IDX_CLUSTER2, 39 PPU_V0_ELEMENT_IDX_CLUSTER3, 40 PPU_V0_ELEMENT_IDX_CLUSTER4, 41 PPU_V0_ELEMENT_IDX_CLUSTER5, 42 PPU_V0_ELEMENT_IDX_CLUSTER6, 43 PPU_V0_ELEMENT_IDX_CLUSTER7, 44 PPU_V0_ELEMENT_IDX_CLUSTER8, 45 PPU_V0_ELEMENT_IDX_CLUSTER9, 46 PPU_V0_ELEMENT_IDX_CLUSTER10, 47 PPU_V0_ELEMENT_IDX_CLUSTER11, 48 49 PPU_V0_ELEMENT_IDX_SYS3, 50 PPU_V0_ELEMENT_IDX_SYS1, 51 PPU_V0_ELEMENT_IDX_SYS2, 52 /* PPU_SYS4 is always ON and managed by romfw */ 53 PPU_V0_ELEMENT_IDX_DEBUG, 54 PPU_V0_ELEMENT_IDX_SYSTOP, 55 56 PPU_V0_ELEMENT_IDX_COUNT 57 }; 58 59 #endif /* CONFIG_PPU_V0_H */ 60