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Searched refs:REG0 (Results 1 – 5 of 5) sorted by relevance

/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/
A Djuno_soc_clock_ram_pll.c46 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in juno_soc_clock_ram_pll_init()
68 pll->REG0 = PLL_REG0_PLL_RESET | in juno_soc_clock_ram_pll_set()
77 pll->REG0 &= ~PLL_REG0_PLL_RESET; in juno_soc_clock_ram_pll_set()
98 feedback_div = ((pll->REG0 & PLL_REG0_NF) >> PLL_REG0_NF_POS) + 1; in juno_soc_clock_ram_pll_get()
/SCP-firmware-master/product/juno/scp_romfw_bypass/
A Djuno_pll_workaround.c36 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in __wrap_arch_exception_reset()
/SCP-firmware-master/product/juno/module/juno_hdlcd/src/
A Dmod_juno_hdlcd.c116 ctx->config->lookup_table[ctx->index].pll.REG0, in enable_pll()
124 SCC->PLL[PLL_IDX_HDLCD].REG0 = in enable_pll()
125 ctx->config->lookup_table[ctx->index].pll.REG0; in enable_pll()
247 SCC->PLL[PLL_IDX_HDLCD].REG0 = (PLL_REG0_PLL_RESET | PLL_REG0_HARD_BYPASS); in juno_hdlcd_set_rate()
450 nf = ((SCC->PLL[PLL_IDX_HDLCD].REG0 & PLL_REG0_NF) >> PLL_REG0_NF_POS) + 1; in juno_hdlcd_start()
/SCP-firmware-master/product/juno/module/juno_soc_clock/src/
A Dmod_juno_soc_clock.c81 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in pll_init()
/SCP-firmware-master/product/juno/include/
A Djuno_scc.h30 FWK_RW uint32_t REG0; member

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