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Searched refs:REG1 (Results 1 – 3 of 3) sorted by relevance

/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/
A Djuno_soc_clock_ram_pll.c72 pll->REG1 = in juno_soc_clock_ram_pll_set()
80 while ((pll->REG1 & PLL_REG1_LOCK_STATUS) == (uint32_t)0) { in juno_soc_clock_ram_pll_set()
99 ref_div = ((pll->REG1 & PLL_REG1_NR) >> PLL_REG1_NR_POS) + 1; in juno_soc_clock_ram_pll_get()
100 output_div = ((pll->REG1 & PLL_REG1_OD) >> PLL_REG1_OD_POS) + 1; in juno_soc_clock_ram_pll_get()
/SCP-firmware-master/product/juno/module/juno_hdlcd/src/
A Dmod_juno_hdlcd.c117 ctx->config->lookup_table[ctx->index].pll.REG1); in enable_pll()
122 SCC->PLL[PLL_IDX_HDLCD].REG1 = in enable_pll()
123 ctx->config->lookup_table[ctx->index].pll.REG1; in enable_pll()
451 nr = ((SCC->PLL[PLL_IDX_HDLCD].REG1 & PLL_REG1_NR) >> PLL_REG1_NR_POS) + 1; in juno_hdlcd_start()
452 od = ((SCC->PLL[PLL_IDX_HDLCD].REG1 & PLL_REG1_OD) >> PLL_REG1_OD_POS) + 1; in juno_hdlcd_start()
/SCP-firmware-master/product/juno/include/
A Djuno_scc.h31 FWK_RW uint32_t REG1; member

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