1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef INTERNAL_RESET_H 9 #define INTERNAL_RESET_H 10 11 typedef enum { RST_TYPE_ALL = 0, RST_TYPE_WO_BUS, RST_TYPE_BUS } RST_TYPE_t; 12 13 typedef enum { 14 RST_PCIE_TOP = 0, 15 RST_PCIE0, 16 RST_PCIE1, 17 RST_DMA, 18 RST_DDR 19 } RST_BLOCK; 20 21 #define RST_ADDR_SYSOC_BUS 0x48300000 22 #define RST_ADDR_SYSOC_SCP 0x48300010 23 #define RST_ADDR_SYSOC_DMA 0x48300040 24 #define RST_ADDR_SYSOC_PCIE 0x48300050 25 #define RST_ADDR_SYSOC_DDR 0x48300060 26 27 #define RST_SYSOC_BUS_TOP 0x00000001 28 #define RST_SYSOC_BUS_PCIE0 0x00000004 29 #define RST_SYSOC_BUS_PCIE1 0x00000002 30 #define RST_SYSOC_BUS_PCIE_TOP 0x00000008 31 32 #define RST_SYSOC_SCP_SCB 0x00000001 33 #define RST_SYSOC_SCP_SCBM 0x00000002 34 #define RST_SYSOC_SCP_CSS_PORST 0x00000004 35 #define RST_SYSOC_SCP_CSS_SYSRST 0x00000008 36 #define RST_SYSOC_SCP_CSS_SRST 0x00000010 37 38 #define RST_SYSOC_DMA_DMA 0x00000001 39 #define RST_SYSOC_DMA_DMAB 0x00000002 40 41 #define RST_SYSOC_PCIE_PCIE0 0x00000002 42 #define RST_SYSOC_PCIE_PCIE1 0x00000001 43 44 #define RST_SYSOC_DDR 0x00000001 45 46 #define RST_ADDR_LPCM_SCB 0x48318400 47 #define RST_ADDR_LPCM_PCIE 0x48319400 48 #define RST_ADDR_LPCM_DMA 0x4831A400 49 50 #define RST_LPCM_SCB_BUS 0x00000001 51 #define RST_LPCM_PCIE0 0x00000002 52 #define RST_LPCM_PCIE1 0x00000001 53 #define RST_LPCM_PCIE0_BUS 0x00000020 54 #define RST_LPCM_PCIE1_BUS 0x00000010 55 #define RST_LPCM_PCIE_TOP 0x00000040 56 #define RST_LPCM_DMA_BUS 0x00000001 57 #define RST_LPCM_DMAB 0x00000002 58 59 #define RST_NO_USE 0 60 61 #define RESET_INFO \ 62 { \ 63 { \ 64 /* PCIe TOP */ /* block sosoc */ RST_NO_USE, \ 65 /* block lpcm */ RST_NO_USE, \ 66 /* bus sosoc */ RST_SYSOC_BUS_PCIE_TOP, \ 67 /* bus lpcm */ RST_LPCM_PCIE_TOP, \ 68 /* addr sysoc blk */ RST_NO_USE, \ 69 /* addr sysoc bus */ RST_ADDR_SYSOC_BUS, \ 70 /* addr lpcm */ RST_ADDR_LPCM_PCIE, \ 71 }, \ 72 { \ 73 /* PCIe PCIe0 */ /* block sosoc */ RST_SYSOC_PCIE_PCIE0, \ 74 /* block lpcm */ RST_LPCM_PCIE0, \ 75 /* bus sosoc */ RST_SYSOC_BUS_PCIE0, \ 76 /* bus lpcm */ RST_LPCM_PCIE0_BUS, \ 77 /* addr sysoc blk */ RST_ADDR_SYSOC_PCIE, \ 78 /* addr sysoc bus */ RST_ADDR_SYSOC_BUS, \ 79 /* addr lpcm */ RST_ADDR_LPCM_PCIE, \ 80 }, \ 81 { \ 82 /* PCIe PCIe1 */ /* block sosoc */ RST_SYSOC_PCIE_PCIE1, \ 83 /* block lpcm */ RST_LPCM_PCIE1, \ 84 /* bus sosoc */ RST_SYSOC_BUS_PCIE1, \ 85 /* bus lpcm */ RST_LPCM_PCIE1_BUS, \ 86 /* addr sysoc blk */ RST_ADDR_SYSOC_PCIE, \ 87 /* addr sysoc bus */ RST_ADDR_SYSOC_BUS, \ 88 /* addr lpcm */ RST_ADDR_LPCM_PCIE, \ 89 }, \ 90 { \ 91 /* DMA */ /* block sosoc */ RST_SYSOC_DMA_DMAB, \ 92 /* block lpcm */ RST_LPCM_DMAB, \ 93 /* bus sosoc */ RST_SYSOC_DMA_DMA, \ 94 /* bus lpcm */ RST_LPCM_DMA_BUS, \ 95 /* addr sysoc blk */ RST_ADDR_SYSOC_DMA, \ 96 /* addr sysoc bus */ RST_ADDR_SYSOC_DMA, \ 97 /* addr lpcm */ RST_ADDR_LPCM_DMA, \ 98 }, \ 99 { /* DDR */ \ 100 /* block sosoc */ RST_SYSOC_DDR, \ 101 /* block lpcm */ RST_NO_USE, \ 102 /* bus sosoc */ RST_NO_USE, \ 103 /* bus lpcm */ RST_NO_USE, \ 104 /* addr sysoc blk */ RST_ADDR_SYSOC_DDR, \ 105 /* addr sysoc bus */ RST_NO_USE, \ 106 /* addr lpcm */ RST_NO_USE, \ 107 } \ 108 } 109 110 void lpcm_sysoc_reset(RST_TYPE_t type, RST_BLOCK block); 111 void lpcm_sysoc_reset_clear(RST_TYPE_t type, RST_BLOCK block); 112 113 #endif /* INTERNAL_RESET_H */ 114