SCC_CLK_RATE_IOFPGA_TSIF2XCLK (reference) in projects: SCP-firmware-master

Searched refs:SCC_CLK_RATE_IOFPGA_TSIF2XCLK (Results 1 – 6 of 6) sorted by relevance

/SCP-firmware-master/product/n1sdp/scp_ramfw/
A D	config_clock.h	`22 #define SCC_CLK_RATE_IOFPGA_TSIF2XCLK (120 * FWK_MHZ) macro`
A D	config_pik_clock.c	`41 .rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK, 44 .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_IOFPGA_TSIF2XCLK, 466 .initial_rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK,`
/SCP-firmware-master/product/morello/scp_ramfw_fvp/
A D	config_clock.h	`30 #define SCC_CLK_RATE_IOFPGA_TSIF2XCLK (120 * FWK_MHZ) macro`
A D	config_pik_clock.c	`40 .rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK, 43 .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_IOFPGA_TSIF2XCLK, 465 .initial_rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK,`
/SCP-firmware-master/product/morello/scp_ramfw_soc/
A D	config_clock.h	`31 #define SCC_CLK_RATE_IOFPGA_TSIF2XCLK (150 * FWK_MHZ) macro`
A D	config_pik_clock.c	`35 .rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK, 38 .divider = CLOCK_RATE_SYSPLLCLK / SCC_CLK_RATE_IOFPGA_TSIF2XCLK, 479 .initial_rate = SCC_CLK_RATE_IOFPGA_TSIF2XCLK,`

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