1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef SCP_SGI575_MMAP_H
9 #define SCP_SGI575_MMAP_H
10 
11 #include <stdint.h>
12 
13 /*
14  * Top-level base addresses
15  */
16 #define SCP_EXPANSION1_BASE           UINT32_C(0x01000000)
17 #define SCP_EXPANSION2_BASE           UINT32_C(0x21000000)
18 #define SCP_EXPANSION3_BASE           UINT32_C(0x40000000)
19 #define SCP_PERIPHERAL_BASE           UINT32_C(0x44000000)
20 #define SCP_MEMORY_CONTROLLER         UINT32_C(0x4E000000)
21 #define SCP_POWER_PERIPHERAL_BASE     UINT32_C(0x50000000)
22 #define SCP_SYS0_BASE                 UINT32_C(0x60000000)
23 #define SCP_SYS1_BASE                 UINT32_C(0xA0000000)
24 #define SCP_PPB_BASE_INTERNAL         UINT32_C(0xE0000000)
25 #define SCP_PPB_BASE_EXTERNAL         UINT32_C(0xE0040000)
26 
27 /*
28  * Peripherals
29  */
30 #define SCP_REFCLK_CNTCTL_BASE        (SCP_PERIPHERAL_BASE + 0x0000)
31 #define SCP_REFCLK_CNTBASE0_BASE      (SCP_PERIPHERAL_BASE + 0x1000)
32 #define SCP_UART_BASE                 (SCP_PERIPHERAL_BASE + 0x2000)
33 #define SCP_WDOG_BASE                 (SCP_PERIPHERAL_BASE + 0x6000)
34 #define SCP_CS_CNTCONTROL_BASE        (SCP_PERIPHERAL_BASE + 0xA000)
35 #define SCP_MHU_AP_BASE               (SCP_PERIPHERAL_BASE + 0x1000000)
36 #define SCP_MHU_MCP_BASE              (SCP_PERIPHERAL_BASE + 0x1600000)
37 
38 /*
39  * Power control peripherals
40  */
41 #define SCP_PIK_SCP_BASE              (SCP_POWER_PERIPHERAL_BASE + 0x00000)
42 #define SCP_PIK_DEBUG_BASE            (SCP_POWER_PERIPHERAL_BASE + 0x20000)
43 #define SCP_SCP_SENSOR_DEBUG_BASE     (SCP_POWER_PERIPHERAL_BASE + 0x30000)
44 #define SCP_PIK_SYSTEM_BASE           (SCP_POWER_PERIPHERAL_BASE + 0x40000)
45 #define SCP_SENSOR_SYSTEM_BASE        (SCP_POWER_PERIPHERAL_BASE + 0x50000)
46 #define SCP_SENSOR_CLUS0_BASE         (SCP_POWER_PERIPHERAL_BASE + 0x70000)
47 #define SCP_SENSOR_CLUS1_BASE         (SCP_POWER_PERIPHERAL_BASE + 0x90000)
48 #define SCP_PIK_CLUSTER_BASE(n)       ((SCP_POWER_PERIPHERAL_BASE + 0x60000) + \
49                                       ((n) * 0x20000))
50 
51 /*
52  * PPU base address
53  */
54 #define SCP_PPU_SCP_BASE              (SCP_PIK_SCP_BASE + 0x1000)
55 #define SCP_PPU_SYS0_BASE             (SCP_PIK_SYSTEM_BASE + 0x1000)
56 #define SCP_PPU_SYS1_BASE             (SCP_PIK_SYSTEM_BASE + 0x5000)
57 #define SCP_PPU_DEBUG_BASE            (SCP_PIK_DEBUG_BASE + 0x1000)
58 #define SCP_PPU_CLUSTER_BASE(n)       (SCP_PIK_CLUSTER_BASE((n)) + 0x1000)
59 #define SCP_PPU_CORE_BASE(n, m)       (SCP_PPU_CLUSTER_BASE((n)) + \
60                                        ((m) + 1) * 0x1000)
61 
62 /*
63  * System access port 0
64  */
65 #define SCP_CMN600_BASE               (SCP_SYS0_BASE + 0x10000000)
66 
67 /*
68  * System access port 1
69  */
70 #define SCP_TRUSTED_RAM_BASE          (SCP_SYS1_BASE + 0x04000000)
71 #define SCP_NONTRUSTED_RAM_BASE       (SCP_SYS1_BASE + 0x06000000)
72 #define SSC_BASE                      (SCP_SYS1_BASE + 0x2A420000)
73 #define SCP_REFCLK_CNTCONTROL_BASE    (SCP_SYS1_BASE + 0x2A430000)
74 
75 /*
76  * Base addresses of MHU devices
77  */
78 #define SCP_MHU_SCP_AP_NS(cluster)    (SCP_MHU_AP_BASE + \
79                                       (0x10000 * cluster) + 0x020)
80 #define SCP_MHU_AP_SCP_NS(cluster)    (SCP_MHU_AP_BASE + \
81                                       (0x10000 * cluster) + 0x120)
82 #define SCP_MHU_SCP_AP_S(cluster)     (SCP_MHU_AP_BASE + \
83                                       (0x10000 * cluster) + 0x200)
84 #define SCP_MHU_AP_SCP_S(cluster)     (SCP_MHU_AP_BASE + \
85                                       (0x10000 * cluster) + 0x300)
86 
87 #define SCP_MHU_SCP_MCP_NS        (SCP_MHU_MCP_BASE + 0x020)
88 #define SCP_MHU_MCP_SCP_NS        (SCP_MHU_MCP_BASE + 0x120)
89 #define SCP_MHU_SCP_MCP_S         (SCP_MHU_MCP_BASE + 0x200)
90 #define SCP_MHU_MCP_SCP_S         (SCP_MHU_MCP_BASE + 0x300)
91 
92 #endif /* SCP_SGI575_MMAP_H */
93