1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef HSSPI_REG_H
9 #define HSSPI_REG_H
10 
11 #include <fwk_macros.h>
12 
13 #include <stdint.h>
14 
15 struct hsspi_reg {
16     FWK_RW uint32_t MCTRL;
17     FWK_RW uint32_t PCC[4];
18     FWK_R uint32_t TXF;
19     FWK_RW uint32_t TXE;
20     FWK_W uint32_t TXC;
21     FWK_R uint32_t RXF;
22     FWK_RW uint32_t RXE;
23     FWK_W uint32_t RXC;
24     FWK_R uint32_t FAULTF;
25     FWK_W uint32_t FAULTC;
26     FWK_RW uint32_t DMCFG;
27     FWK_RW uint32_t DMCTRL;
28     FWK_RW uint32_t DMBCCS;
29     FWK_R uint32_t DMSTATUS;
30     uint32_t RESERVED[2];
31     FWK_RW uint32_t FIFOCFG;
32     FWK_W uint32_t TXFIFO[16];
33     FWK_R uint32_t RXFIFO[16];
34     FWK_RW uint32_t CSCFG;
35     FWK_RW uint32_t CSITIME;
36     FWK_RW uint32_t CSAEXT;
37     FWK_RW uint32_t RDCSDC[4];
38     FWK_RW uint32_t WRCSDC[4];
39     FWK_R uint32_t MID;
40 };
41 
42 #define MAX_SLAVE_NUM (4)
43 
44 #define DISABLE (0)
45 #define ENABLE  (1)
46 
47 /* MCTRL reigster field */
48 #define MCTRL_MES(val)    (((val)&0x1) << 4)
49 #define MCTRL_MES_MASK    MCTRL_MES(1)
50 #define MCTRL_CDSS(val)   (((val)&0x1) << 3)
51 #define MCTRL_CDSS_MASK   MCTRL_CDSS(1)
52 #define MCTRL_CSEN(val)   (((val)&0x1) << 1)
53 #define MCTRL_CSEN_MASK   MCTRL_CSEN(1)
54 #define MCTRL_MEN(val)    ((val)&0x1)
55 #define MCTRL_MEN_MASK    MCTRL_MEN(1)
56 
57 /* PCC reigster field */
58 #define PCC_RD_DESEL_TIME(val) (((val)&0xF) << 21)
59 #define PCC_RD_DESEL_TIME_MASK PCC_RD_DESEL_TIME(0xF)
60 
61 #define PCC_WR_DESEL_TIME(val) (((val)&0xF) << 17)
62 #define PCC_WR_DESEL_TIME_MASK PCC_WR_DESEL_TIME(0xF)
63 
64 #define PCC_CLOCK_DIV(val) (((val)&0x7F) << 9)
65 #define PCC_CLOCK_DIV_MASK PCC_CLOCK_DIV(0x7F)
66 
67 /* CSCFG reigster field */
68 #define CSCFG_MSEL(val)        (((val)&0xF) << 16)
69 #define CSCFG_MSEL_MASK        CSCFG_MSEL(0xF)
70 #define MEMORY_BANK_SIZE(msel) (0x2000UL << (msel))
71 #define MEMORY_BANK_MASK(msel) ((0x2000UL << (msel)) - 1)
72 
73 #define CSCFG_SSELEN(s0, s1, s2, s3) \
74     ((((s0)&0x1) << 8) | (((s1)&0x1) << 9) | (((s2)&0x1) << 10) | \
75      (((s3)&0x1) << 11))
76 #define CSCFG_SSELEN_MASK CSCFG_SSELEN(1, 1, 1, 1)
77 
78 #define CSCFG_BOOTEN(val) (((val)&0x1) << 4)
79 #define CSCFG_BOOTEN_MASK CSCFG_BOOTEN(0x1)
80 
81 #define CSCFG_SPICHG(val) (((val)&0x1) << 3)
82 #define CSCFG_SPICHG_MASK CSCFG_SPICHG(0x1)
83 
84 #define CSCFG_MBM(val) (((val)&0x3) << 1)
85 #define CSCFG_MBM_MASK CSCFG_MBM(0x3)
86 #define IO_SINGLE      (0x0)
87 #define IO_DUAL        (0x1)
88 #define IO_QUAD        (0x2)
89 
90 #define CSCFG_SRAM(val) ((val)&0x1)
91 #define CSCFG_SRAM_MASK CSCFG_SRAM(0x1)
92 #define READ_ONLY       (0x0)
93 #define WRITABLE        (0x1)
94 
95 /* CSITIME register field */
96 #define CSITIME_MASK (0xFFFF)
97 #define CSITIME_256  (0x100)
98 
99 /* RDCSDC, WRCSDC register field */
100 #define DATA(val)    (((val)&0xFF) << 8)
101 #define TRP(val)     (((val)&0x3) << 1)
102 #define TRP_DEFAULT  (0x0)
103 #define TRP_DUAL     (0x1)
104 #define TRP_QUAD     (0x2)
105 #define TRP_SINGLE   (0x3)
106 #define DEC(val)     ((val)&0x1)
107 #define USE_RAW_DATA (0x0)
108 #define USE_DEC_DATA (0x1)
109 
110 /* Decoded Data */
111 #define MEMORY_ADDR_07_00 (0x0)
112 #define MEMORY_ADDR_15_08 (0x1)
113 #define MEMORY_ADDR_23_16 (0x2)
114 #define MEMORY_ADDR_31_24 (0x3)
115 #define DUMMY_CYCLE_1BYTE (0x4)
116 #define ALT_NIBBLE_FORMAT (0x5)
117 #define DATA_PHASE_START  (0x7)
118 
119 #define SET_RAW_DATA(data, trp) (DATA(data) | TRP(trp) | DEC(USE_RAW_DATA))
120 #define SET_DEC_DATA(data, trp) (DATA(data) | TRP(trp) | DEC(USE_DEC_DATA))
121 #define SET_ALT_NIBBLE(data, trp) \
122     SET_DEC_DATA(((data & 0xF0) | ALT_NIBBLE_FORMAT), trp)
123 #define SET_ADDR_1BYTE(trp)  SET_DEC_DATA(MEMORY_ADDR_07_00, trp)
124 #define SET_ADDR_2BYTE(trp)  SET_DEC_DATA(MEMORY_ADDR_15_08, trp)
125 #define SET_ADDR_3BYTE(trp)  SET_DEC_DATA(MEMORY_ADDR_23_16, trp)
126 #define SET_ADDR_4BYTE(trp)  SET_DEC_DATA(MEMORY_ADDR_31_24, trp)
127 #define SET_DUMMY_1BYTE(trp) SET_DEC_DATA(DUMMY_CYCLE_1BYTE, trp)
128 #define SET_DUMMY_CYCLE_2    SET_DEC_DATA(DUMMY_CYCLE_1BYTE, TRP_QUAD)
129 #define SET_DUMMY_CYCLE_4    SET_DEC_DATA(DUMMY_CYCLE_1BYTE, TRP_DUAL)
130 #define SET_DUMMY_CYCLE_8    SET_DEC_DATA(DUMMY_CYCLE_1BYTE, TRP_SINGLE)
131 #define END_OF_COMMAND(trp)  SET_DEC_DATA(DATA_PHASE_START, trp)
132 
133 #endif /* HSSPI_REG_H */
134