1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SGM776_SDS_H 9 #define SGM776_SDS_H 10 11 #include <mod_sds.h> 12 13 /* 14 * Structure identifiers. 15 */ 16 enum sgm776_sds_struct_id { 17 SGM776_SDS_CPU_INFO = 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 18 SGM776_SDS_ROM_VERSION = 2 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 19 SGM776_SDS_RAM_VERSION = 3 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 20 SGM776_SDS_PLATFORM_ID = 4 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 21 SGM776_SDS_RESET_SYNDROME = 5 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 22 SGM776_SDS_FEATURE_AVAILABILITY = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 23 SGM776_SDS_CPU_BOOTCTR = 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 24 SGM776_SDS_CPU_FLAGS = 8 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 25 SGM776_SDS_BOOTLOADER = 9 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 26 }; 27 28 enum sgm776_sds_region_idx { 29 SGM776_SDS_REGION_SECURE, 30 #ifdef BUILD_MODE_DEBUG 31 SGM776_SDS_REGION_NONSECURE, 32 #endif 33 SGM776_SDS_REGION_COUNT, 34 }; 35 36 /* 37 * Structure sizes. 38 */ 39 #define SGM776_SDS_CPU_INFO_SIZE 4 40 #define SGM776_SDS_ROM_VERSION_SIZE 4 41 #define SGM776_SDS_RAM_VERSION_SIZE 4 42 #define SGM776_SDS_PLATFORM_ID_SIZE 8 43 #define SGM776_SDS_RESET_SYNDROME_SIZE 4 44 #define SGM776_SDS_FEATURE_AVAILABILITY_SIZE 4 45 #define SGM776_SDS_CPU_BOOTCTR_SIZE 8 46 #define SGM776_SDS_CPU_FLAGS_SIZE 8 47 #define SGM776_SDS_BOOTLOADER_SIZE 12 48 49 /* 50 * Field masks and offsets for the SGM776_SDS_AP_CPU_INFO structure. 51 */ 52 #define SGM776_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF 53 #define SGM776_SDS_CPU_INFO_PRIMARY_POS 0 54 55 /* 56 * Structure, field masks and offsets for the SGM776_SDS_PLATFORM_ID structure. 57 */ 58 59 struct sgm776_sds_platid { 60 uint32_t platform_identifier; 61 uint32_t platform_type_identifier; 62 }; 63 64 #define SGM776_SDS_PLATID_PARTNO_MASK 0xFFF 65 #define SGM776_SDS_PLATID_DESIGNER_MASK 0xFF000 66 #define SGM776_SDS_PLATID_REV_MINOR_MASK 0xF00000 67 #define SGM776_SDS_PLATID_REV_MAJOR_MASK 0xF000000 68 #define SGM776_SDS_PLATID_CONFIG_MASK 0xF0000000 69 #define SGM776_SDS_PLATID_TYPE_MASK 0xF 70 71 #define SGM776_SDS_PLATID_PARTNO_POS 0 72 #define SGM776_SDS_PLATID_DESIGNER_POS 12 73 #define SGM776_SDS_PLATID_REV_MINOR_POS 20 74 #define SGM776_SDS_PLATID_REV_MAJOR_POS 24 75 #define SGM776_SDS_PLATID_CONFIG_POS 28 76 77 #define SGM776_SDS_PLATID_TYPE_POS 0 78 /* 79 * Field masks and offsets for the SGM776_SDS_RESET_SYNDROME structure. 80 */ 81 #define SGM776_SDS_RESET_SYNDROME_POR_MASK 0x1 82 #define SGM776_SDS_RESET_SYNDROME_WDOGSCP_MASK 0x2 83 #define SGM776_SDS_RESET_SYNDROME_WDOGAP_MASK 0x4 84 #define SGM776_SDS_RESET_SYNDROME_SYSRESET_MASK 0x8 85 #define SGM776_SDS_RESET_SYNDROME_M3LOCKUP_MASK 0x10 86 87 #define SGM776_SDS_RESET_SYNDROME_POR_POS 0 88 #define SGM776_SDS_RESET_SYNDROME_WDOGSCP_POS 1 89 #define SGM776_SDS_RESET_SYNDROME_WDOGAP_POS 2 90 #define SGM776_SDS_RESET_SYNDROME_SYSRESET_POS 3 91 #define SGM776_SDS_RESET_SYNDROME_M3LOCKUP_POS 4 92 93 /* 94 * Field masks and offsets for the SGM776_SDS_FEATURE_AVAILABILITY structure. 95 */ 96 #define SGM776_SDS_FEATURE_FIRMWARE_MASK 0x1 97 #define SGM776_SDS_FEATURE_DMC_MASK 0x2 98 #define SGM776_SDS_FEATURE_MESSAGING_MASK 0x4 99 100 #define SGM776_SDS_FEATURE_FIRMWARE_POS 0 101 #define SGM776_SDS_FEATURE_DMC_POS 1 102 #define SGM776_SDS_FEATURE_MESSAGING_POS 2 103 104 /* 105 * Field masks and offsets for the SGM776_SDS_CPU_BOOTCTR structure. 106 */ 107 #define SGM776_SDS_CPU_BOOTCTR_CPU0_MASK 0xFF 108 #define SGM776_SDS_CPU_BOOTCTR_CPU1_MASK 0xFF00 109 #define SGM776_SDS_CPU_BOOTCTR_CPU2_MASK 0xFF0000 110 #define SGM776_SDS_CPU_BOOTCTR_CPU3_MASK 0xFF000000 111 #define SGM776_SDS_CPU_BOOTCTR_CPU4_MASK 0xFF 112 #define SGM776_SDS_CPU_BOOTCTR_CPU5_MASK 0xFF00 113 #define SGM776_SDS_CPU_BOOTCTR_CPU6_MASK 0xFF0000 114 #define SGM776_SDS_CPU_BOOTCTR_CPU7_MASK 0xFF000000 115 116 117 #define SGM776_SDS_CPU_BOOTCTR_CPU0_POS 0 118 #define SGM776_SDS_CPU_BOOTCTR_CPU1_POS 8 119 #define SGM776_SDS_CPU_BOOTCTR_CPU2_POS 16 120 #define SGM776_SDS_CPU_BOOTCTR_CPU3_POS 24 121 #define SGM776_SDS_CPU_BOOTCTR_CPU4_POS 0 122 #define SGM776_SDS_CPU_BOOTCTR_CPU5_POS 8 123 #define SGM776_SDS_CPU_BOOTCTR_CPU6_POS 16 124 #define SGM776_SDS_CPU_BOOTCTR_CPU7_POS 24 125 126 /* 127 * Field masks and offsets for the SGM776_SDS_CPU_FLAGS structure. 128 */ 129 #define SGM776_SDS_CPU_FLAGS_CPU0_WFI_MASK 0x1 130 #define SGM776_SDS_CPU_FLAGS_CPU1_WFI_MASK 0x100 131 #define SGM776_SDS_CPU_FLAGS_CPU2_WFI_MASK 0x10000 132 #define SGM776_SDS_CPU_FLAGS_CPU3_WFI_MASK 0x1000000 133 #define SGM776_SDS_CPU_FLAGS_CPU4_WFI_MASK 0x1 134 #define SGM776_SDS_CPU_FLAGS_CPU5_WFI_MASK 0x100 135 #define SGM776_SDS_CPU_FLAGS_CPU6_WFI_MASK 0x10000 136 #define SGM776_SDS_CPU_FLAGS_CPU7_WFI_MASK 0x1000000 137 138 #define SGM776_SDS_CPU_FLAGS_CPU0_WFI_POS 0 139 #define SGM776_SDS_CPU_FLAGS_CPU1_WFI_POS 8 140 #define SGM776_SDS_CPU_FLAGS_CPU2_WFI_POS 16 141 #define SGM776_SDS_CPU_FLAGS_CPU3_WFI_POS 24 142 #define SGM776_SDS_CPU_FLAGS_CPU4_WFI_POS 0 143 #define SGM776_SDS_CPU_FLAGS_CPU5_WFI_POS 8 144 #define SGM776_SDS_CPU_FLAGS_CPU6_WFI_POS 16 145 #define SGM776_SDS_CPU_FLAGS_CPU7_WFI_POS 24 146 /* 147 * Field masks and offsets for the SGM776_SDS_BOOTLOADER structure. 148 */ 149 #define SGM776_SDS_BOOTLOADER_VALID_MASK 0x1 150 #define SGM776_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF 151 #define SGM776_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF 152 153 #define SGM776_SDS_BOOTLOADER_VALID_POS 0 154 #define SGM776_SDS_BOOTLOADER_OFFSET_POS 0 155 #define SGM776_SDS_BOOTLOADER_SIZE_POS 0 156 157 #endif /* SGM776_SDS_H */ 158