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Searched refs:bit (Results 1 – 22 of 22) sorted by relevance

/SCP-firmware-master/product/rcar/scp_ramfw/
A Dconfig_rcar_mstp_clock.c24 .bit = 18,
31 .bit = 19,
38 .bit = 2,
45 .bit = 3,
52 .bit = 4,
59 .bit = 6,
66 .bit = 7,
73 .bit = 8,
80 .bit = 9,
129 .bit = 0,
[all …]
A Dconfig_rcar_reset.c19 .bit = 18,
26 .bit = 19,
33 .bit = 2,
40 .bit = 3,
47 .bit = 4,
54 .bit = 6,
61 .bit = 7,
68 .bit = 8,
75 .bit = 9,
124 .bit = 0,
[all …]
/SCP-firmware-master/product/morello/module/dmc_bing/src/
A Dmorello_ddr_phy.c291 uint32_t bit; in write_eye_detect_single_rank() local
338 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
359 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit += 2) { in write_eye_detect_single_rank()
393 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
412 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
414 if (bit % 2 == 1) { in write_eye_detect_single_rank()
474 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
495 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
541 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
594 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
[all …]
/SCP-firmware-master/product/n1sdp/module/n1sdp_ddr_phy/src/
A Dmod_n1sdp_ddr_phy.c363 uint32_t bit; in write_eye_detect_single_rank() local
410 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
431 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit += 2) { in write_eye_detect_single_rank()
467 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
486 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
488 if (bit % 2 == 1) { in write_eye_detect_single_rank()
551 bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
572 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
618 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
667 for (bit = 0; bit < NUM_BITS_PER_SLICE; bit++) { in write_eye_detect_single_rank()
[all …]
/SCP-firmware-master/product/rcar/module/rcar_reset/src/
A Dmod_rcar_reset.c44 BIT(ctx->config->bit)); in rcar_auto_domain()
51 BIT(ctx->config->bit)); in rcar_auto_domain()
63 BIT(ctx->config->bit)); in rcar_assert_domain()
75 BIT(ctx->config->bit)); in rcar_deassert_domain()
/SCP-firmware-master/product/synquacer/module/synquacer_memc/include/internal/
A Dreg_DMA330.h64 } bit; member
77 } bit; member
92 } bit; member
109 } bit; member
132 } bit; member
/SCP-firmware-master/arch/arm/armv8-a/src/
A Darch_gic.c404 unsigned int bit; in is_pending() local
409 bit = interrupt % 32; in is_pending()
411 ((gicd_read_ispendr(RCAR_GICD_BASE, interrupt) & (1 << bit)) ? true : in is_pending()
419 unsigned int bit; in set_pending() local
424 bit = interrupt % 32; in set_pending()
425 gicd_write_ispendr(RCAR_GICD_BASE, interrupt, 1U << bit); in set_pending()
432 unsigned int bit; in clear_pending() local
437 bit = interrupt % 32; in clear_pending()
438 gicd_write_icpendr(RCAR_GICD_BASE, interrupt, 1U << bit); in clear_pending()
/SCP-firmware-master/product/rcar/module/rcar_mstp_clock/src/
A Dmod_rcar_mstp_clock.c44 value &= ~(BIT(ctx->config->bit)); in mstp_clock_set_state()
46 value |= BIT(ctx->config->bit); in mstp_clock_set_state()
53 BIT(ctx->config->bit))) in mstp_clock_set_state()
80 BIT(ctx->config->bit)) in mstp_clock_hw_initial_set_state()
/SCP-firmware-master/product/rcar/module/rcar_reset/include/
A Dmod_rcar_reset.h43 volatile uint32_t const bit; member
/SCP-firmware-master/module/scmi_apcore/doc/
A Dscmi_apcore.md62 * Bit [0] If set to 1, the platform supports 64-bit reset addresses. If set
63 to 0, the platform supports 32-bit reset addresses.
111 * On platforms that support only 32-bit addresses, only the lower word is
113 aligned. For platforms supporting 64-bit addresses both words may be used
125 * Platform supports only 32-bit addresses and the reset address received
152 * On platforms that support only 32-bit addresses, only the lower word is
/SCP-firmware-master/product/rcar/module/rcar_mstp_clock/include/
A Dmod_rcar_mstp_clock.h39 volatile uint32_t const bit; member
/SCP-firmware-master/product/synquacer/module/f_i2c/include/internal/
A Di2c_driver.h44 } bit; member
/SCP-firmware-master/module/apremap/doc/
A Dmodule_apremap_design.md10 Reference Design platforms are based on 32-bit Cortex-M7 processor and can
120 application processor address space, the `CMN_ATRANS_EN` bit in SCP PIK register
122 Setting this bit will translate MSCP's `0x6000_0000 - 0x9FFF_FFFFF` to
/SCP-firmware-master/cmake/Toolchain/
A DArmClang-Base.cmake37 # bit of a hacky workaround to reset it to nothing whenever the CMake toolchain
/SCP-firmware-master/doc/
A Dcode_rules.md334 - Avoid C structure bit-fields when representing hardware registers - how
335 bit-fields are represented in memory is implementation-defined.
337 - Bit definitions must be prefixed by the register name it relates to. If bit
360 /* Register bit definitions */
A DDoxyfile1009 # will make the HTML file larger and loading of large files a bit slower, you
/SCP-firmware-master/module/mpmm/doc/
A Dmodule_mpmm.md48 The Threshold map is a 32-bit value. Each 4-bits represents the threshold state
/SCP-firmware-master/product/synquacer/module/f_i2c/src/
A Di2c_driver.c240 addr.bit.BITFIELD_READ = read; in i2c_packet_set_control()
241 addr.bit.BITFIELD_ADDR = (uint8_t)address; in i2c_packet_set_control()
/SCP-firmware-master/module/i2c/doc/
A Dmodule_i2c_architecture.md35 - 10-bit target addressing.
/SCP-firmware-master/debugger/src/cli/
A Dreadme.txt88 l Used within a specifier, indicates 64 bit value.
/SCP-firmware-master/
A Duser_guide.md15 This software has been tested on Ubuntu 20.04 LTS (64-bit).
A Dchange_log.md157 - sgi575/rdn1e1/rdv1/rdv1mc: add cmn650 mapping for 64-bit pcie mmio address space

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